2

Pin Configuration and Functionality

2.1

Pin Configuration

Table 1

Pin Configuration

Pin No.

Name

Function

1

VCC1

Positive logic supply

2

IN+

Non-inverted driver input (active high)

3

IN-

Inverted driver input (active low)

4

GND1

Logic ground

5

GND2

Power ground

6

VCC2

Positive power supply voltage

7

OUT

Driver output

8

CLAMP

Active Miller clamp

1

2

3

4

8

7

6

5

VCC1

IN+

IN-

GND1

CLAMP

OUT

VCC2

GND2

Figure 2

PG-DSO-8-59 (top view)

2.2

Pin Functionality

VCC1

Logic input supply voltage of 3.3 V up to 15 V wide operating range.

IN+ Non Inverting Driver Input

IN+ non-inverted control signal for driver output if IN- is set to low. (Output sourcing active at IN+ = high and IN-

= low)

Due to internal filtering a minimum pulse width is defined to ensure robustness against noise at IN+. An internal

weak pull-down-resistor favors off-state.

IN- Inverting Driver Input

IN- inverted control signal for driver output if IN+ is set to high. (Output sourcing active at IN- = low and IN

+ = high)

Single channel IGBT gate driver IC with clamp in wide body package

Pin Configuration and Functionality

Datasheet

4

Rev. 2.0

2016-07-05