WT6018

Digital Monitor Controller

Ver. 1.41 Jul-31-1998

Weltrend Semiconductor, Inc.

7

Port_C :

Pin PC0 - general purpose I/O pin shared with 4-bit A/D converter 0 input.

Pin PC1 - general purpose I/O pin shared with 4-bit A/D converter 1 input

Pin PC2 to PC7 - general purpose I/O pins.

The REG#14H defines the I/O direction and the REG#15H controls the output level.

The structure of Port_C is same as the Port_B except the sink current is 10mA. When PC0 and

PC1 are programmed as the A/D converter inputs, the pull high transistor is disconnected.

Address

R/W

Initial

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0014H

W

00H

PC7OE PC6OE PC5OE PC4OE PC3OE PC2OE PC1OE PC0OE

0015H

W

FFH

PC7W

PC6W

PC5W

PC4W

PC3W

PC2W

PC1W

PC0W

0015H

R

--

PC7R

PC6R

PC5R

PC4R

PC3R

PC2R

PC1R

PC0R

Bit Name

Bit value = “1”

Bit value = “0”

PC7OE - PC0OE

Output enable.

Output disable (internal pull-up).

PC7W - PC0W

PC7R - PC0R

Pin is high level.

Pin is low level.

Port_D :

Pin SCL/PD0

- general purpose I/O pin shared with DDC interface serial clock.

Pin SDA/PD1

- general purpose I/O pin shared with DDC interface serial data.

The structure of these two pins are same as the PB4 and PB5. Default is DDC interface and can be

changed to I/O port D by setting ENPD bit.

Address

R/W

Initial

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

000FH

W

00H

--

--

--

ENPD

PD1OE PD0OE PD1W

PD0W

000FH

R

--

--

--

--

--

--

--

PD1R

PD0R

Bit Name

Bit value = “1”

Bit value = “0”

ENPD

Enable I/O Port_D.

DDC interface.(open drain)

PD1OE - PD0OE

Output enable.

Output disable (internal pull-up).

PD1W - PD0W

PD1R- PD0R

Pin is high level.

Pin is low level.

* If program wants to read current status on the I/O pins (any I/O port), do not set output enable bit to

“0”. Because the registers for reading I/O are always indicating the current state on the I/O pins, set

output enable bit to “0” will change the level on the I/O pin. Please reference the I/O pin structure.