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UCC27221 Datasheet(PDF) 4 Page - Texas Instruments |
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UCC27221 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 27 page UCC27221 UCC27222 SLUS486B − AUGUST 2001 − REVISED JULY 2003 4 www.ti.com ELECTRICAL CHARACTERISTICS VDD = 12-V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VHI to SW, 0.1-µF and 2.2-µF capacitor from PVLO to PGND, PVLO tied to VLO, TA = −40_C to 105_C for the UCC2722x, TA = TJ (unless otherwise noted) G1 main output PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Sink resistance SW = 0 V, VHI = 6 V, IN = 0 V, G1 = 0.5 V 0.3 0.9 1.5 Ω Source resistance(2) SW = 0 V, VHI = 6 V, IN = 6.5 V, G1 = 5.5 V 10 25 45 Ω Source current(1)(2) SW = 0 V, VHI = 6 V, IN = 6.5 V, G1 = 3.0 V −3 −3.3 A Sink current(1)(2) SW = 0 V, VHI = 6 V, IN = 0 V, G1 = 3.0 V 3 3.3 A Rise time C = 2.2 nF from G1 to SW, VDD = 20 V 17 25 ns Fall time C = 2.2 nF from G1 to SW, VDD = 20 V 17 25 ns G2 SR output PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Sink resistance(2) PVLO = 6.5 V, IN = 6.5 V, G1 = 0.25 V 5 15 30 Ω Source resistance(2) PVLO = 6.5 V, IN = 0 V, G2 = 6.0 V 10 20 35 Ω Source current(1)(2) PVLO = 6.5 V, IN = 0 V G2 = 3.25 V −3 −3.3 A Sink current(1)(2) PVLO = 6.5 V, IN = 6.5 V G2 = 3.25 V 3 3.3 A Rise time(2) C = 2.2 nF from G2 to PGND VDD = 20 V 17 25 ns Fall time C = 2.2 nF from G2 to PGND VDD = 20 V 20 35 ns deadtime delay PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tOFF, G2, IN to G2 falling 60 80 100 tOFF, G1, IN to G1 falling 55 80 110 Delay Step Resolution 3.5 4.1 4.7 tON, G1 minimum −15 ns tON, G1 maximum 48 ns tON, G2 minimum −21 tON, G2 maximum 38 NOTE 1: Ensured by design. Not production tested. 2: The pullup / pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. UDG−01042 UCC27222 tOFF,G1 tOFF,G2 tON,G1 tON,G2 IN G1 G2 3.25 V 10% 90% 90% 10% Figure 1. Predictive Gate Drive Timing Diagram |
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