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9FGV0631CKLF Datasheet(PDF) 1 Page - Integrated Device Technology |
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9FGV0631CKLF Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 15 page DATASHEET 9FGV0631C OCTOBER 18, 2016 1 ©2016 Integrated Device Technology, Inc. 6-O/P 1.8V PCIe Gen 1-2-3 Clock Generator 9FGV0631C General Description The 9FGV0631C is a member of IDT's SOC-Friendly 1.8V Very-Low-Power PCIe clock family. The device has 6 output enables for clock management, 2 different spread spectrum levels in addition to spread off and 2 selectable SMBus addresses. Recommended Application 1.8V PCIe Gen 1-2-3 Clock Generator Output Features • 6 - 100MHz Low-Power (LP) HCSL DIF pairs • 1 - 1.8V LVCMOS REF output w/Wake-On-LAN (WOL) support Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps • DIF phase jitter is PCIe Gen1-2-3 Compliant • REF phase jitter is <1.5ps RMS Features/Benefits • LP-HCSL outputs; save 12 resistors compared to standard PCIe devices • 54mW typical power consumption; reduced thermal concerns • Outputs can optionally be supplied from any voltage between 1.05V and 1.8V; maximum power savings • OE# pins; support DIF power management • Programmable Slew rate for each output; allows tuning for various line lengths • Programmable output amplitude; allows tuning for various application environments • DIF outputs blocked until PLL is locked; clean system start-up • Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI • External 25MHz crystal; supports tight ppm with 0 ppm synthesis error • Configuration can be accomplished with strapping pins; SMBus interface not required for device control • 3.3V tolerant SMBus interface works with legacy controllers • Selectable SMBus addresses; multiple devices can easily share an SMBus segment • Space saving 40-pin 5x5 mm VFQFPN; minimal board space Block Diagram XIN/CLKIN_25 X2 CONTROL LOGIC vSS_EN_tri ^CKPWRGD_PD# SDATA_3.3 SS Capable PLL OSC REF1.8 vOE(5:0)# SCLK_3.3 vSADR DIF5 DIF4 DIF3 DIF2 DIF1 DIF0 |
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