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9FGU0431AKILF Datasheet(PDF) 7 Page - Integrated Device Technology |
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9FGU0431AKILF Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 15 page OCTOBER 18, 2016 7 4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR 9FGU0431 DATASHEET Electrical Characteristics–DIF Low-Power HCSL Outputs Electrical Characteristics–DIF Output Phase Jitter Parameters TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Scope averaging on fast setting 1.1 2.2 3.3 V/ns 1,2,3 Scope averaging on slow setting 0.9 1.7 2.6 V/ns 1,2,3 Slew rate matching ΔTrf Slew rate matching, Scope averaging on 3 20 % 1,2,4 Voltage High VHIGH 600 735 850 7 Voltage Low VLOW -150 -16 150 7 Max Voltage Vmax 779 1150 7 Min Voltage Vmin -300 -45 7 Vswing Vswing Scope averaging off 300 1503 mV 1,2,7 Crossing Voltage (abs) Vcross_abs Scope averaging off 250 405 550 mV 1,5,7 Crossing Voltage (var) Δ-Vcross Scope averaging off 12 140 mV 1,6,7 2 Measured from differential waveform 7 At default SMBus amplitude settings. 1Guaranteed by design and characterization, not 100% tested in production. 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute. Slew rate Trf Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) mV Measurement on single ended signal using absolute value. (Scope averaging off) mV TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX IND. LIMIT UNITS Notes tjphPCIeG1 PCIe Gen 1 27.7 40 86 ps (p-p) 1,2,3,5 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz 1.0 1.3 3 ps (rms) 1,2,3,5 PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) 1.9 2.2 3.1 ps (rms) 1,2,3,5 tjphPCIeG3 PCIe Gen 3 Common Clock Architecture (PLL BW of 2-4 or 2-5MHz, CDR = 10MHz) 0.4 0.6 1 ps (rms) 1,2,3,5 tjphPCIeG3SRn S PCIe Gen 3 Separate Reference No Spread (SRnS) (PLL BW of 2-4 or 2-5MHz, CDR = 10MHz) 0.4 0.6 0.7 ps (rms) 1,2,3,5 1 Guaranteed by design and characterization, not 100% tested in production. 5 Applies to all differential outputs Phase Jitter, PLL Mode tjphPCIeG2 2 See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 Calculated from Intel-supplied Clock Jitter Tool |
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