OCTOBER 18, 2016

7

4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR

9FGU0431 DATASHEET

Electrical Characteristics–DIF Low-Power HCSL Outputs

Electrical Characteristics–DIF Output Phase Jitter Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Scope averaging on fast setting

1.1

2.2

3.3

V/ns

1,2,3

Scope averaging on slow setting

0.9

1.7

2.6

V/ns

1,2,3

Slew rate matching

ΔTrf

Slew rate matching, Scope averaging on

3

20

%

1,2,4

Voltage High

600

735

850

7

Voltage Low

-150

-16

150

7

Max Voltage

Vmax

779

1150

7

Min Voltage

Vmin

-300

-45

7

Vswing

Vswing

Scope averaging off

300

1503

mV

1,2,7

Crossing Voltage (abs)

Vcross_abs

Scope averaging off

250

405

550

mV

1,5,7

Crossing Voltage (var)

Δ-Vcross

Scope averaging off

12

140

mV

1,6,7

differential 0V.

the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations.

edge (i.e. Clock rising and Clock# falling).

absolute) allowed. The intent is to limit Vcross induced modulation by setting

Δ-Vcross to be smaller than Vcross absolute.

Slew rate

Trf

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope

averaging on)

mV

Measurement on single ended signal using

absolute value. (Scope averaging off)

mV

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

IND.

LIMIT

UNITS

Notes

PCIe Gen 1

27.7

40

86

ps (p-p) 1,2,3,5

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

1.0

1.3

3

ps

(rms)

1,2,3,5

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

1.9

2.2

3.1

ps

(rms)

1,2,3,5

PCIe Gen 3 Common Clock Architecture

(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)

0.4

0.6

1

ps

(rms)

1,2,3,5

S

PCIe Gen 3 Separate Reference No Spread (SRnS)

(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)

0.4

0.6

0.7

ps

(rms)

1,2,3,5

Phase Jitter, PLL Mode