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PS9551AL4-V-E3-AX Datasheet(PDF) 5 Page - California Eastern Labs |
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PS9551AL4-V-E3-AX Datasheet(HTML) 5 Page - California Eastern Labs |
5 / 20 page PS9551AL4 Chapter Title R08DS0121EJ0100 Rev.1.00 Page 5 of 18 Mar 20, 2014 ELECTRICAL CHARACTERISTICS (TYP.: TA = 25 °C, VIN+ = VIN− = 0 V, VDD1 = VDD2 = 5 V, MIN., MAX.: refer to RECOMMENDED OPERATING CONDITIONS, unless otherwise specified) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input Supply Current IDD1 VIN+ = 350 mV 12 15 mA Output Supply Current IDD2 VIN+ = −350 mV 6 15 mA Input Bias Current IIN −5 −0.6 5 μA Low Level Saturated Output Voltage VOL IOUT = 1.6 mA 0.1 0.6 V High Level Saturated Output Voltage VOH IOUT = −100 μA 3.9 4.9 V Output Short-circuit Current |IOSC| VOUT = VDD2 or VOUT = GND2 17 40 mA Equivalent Input Resistance RIN 450 k Ω Output Clock Frequency fCLK 8.2 10 13.2 MHz Isolation Resistance RI-O VI-O = 1 kVDC, TA = 25 °C 10 11 Ω Isolation Capacitance CI-O f = 1 MHz 0.7 pF Data Hold Time *1 tHDDAT 4 10 16 ns Common Mode Transient Immunity *2 CMR VCM = 1 kV, TA = 25 °C 15 kV/ μs *1 The data hold time (tHDDAT) is that the data (MDAT) will stay stable following the rising edge of the clock (MCLK). tHDDAT is shown in the below timing chart. Fig. Timing Chart *2 Common Mode Transient Immunity (CMR) is specified by the rate of rise / fall of a pulse applied between GND1 on the input side and GND2 on the output side (pins 4 and 5) by using the circuit shown in Fig. 6 CMR Test Circuit. CMR is defined at the point that clock signals are corrupted. MCLK MDAT tHDDAT <R> A Business Partner of Renesas Electronics Corporation. |
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