9DBV0541 datasheet(7/17 Pages) IDT

Part #	9DBV0541

Description	5-output 1.8V HCSL Fanout Buffer

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Manufacturer	IDT [Integrated Device Technology]

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REVISION D 05/23/16

7

5-OUTPUT 1.8V HCSL FANOUT BUFFER W/ZO=100OHMS

9DBV0541 DATASHEET

Electrical Characteristics–DIF Low Power HCSL Outputs

Electrical Characteristics–Current Consumption

TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Scope averaging on, fast slew rate setting

1.6

2.6

4.3

V/ns

1,2,3

Scope averaging on, slow slew rate setting

1.2

2.0

3.2

V/ns

1,2,3

Slew rate matching

ΔTrf

Slew rate matching, Scope averaging on

6

20

%

1,2,4

Voltage High

VHIGH

660

758

850

7

Voltage Low

VLOW

-150

43

150

7

Max Voltage

Vmax

775

1150

7

Min Voltage

Vmin

-300

12

7

Vswing

Scope averaging off

300

1428

mV

1,2

Crossing Voltage (abs)

Vcross_abs

Scope averaging off

250

391

550

mV

1,5

Crossing Voltage (var)

Δ-Vcross

Scope averaging off

14

140

mV

1,6

2 Measured from differential waveform

7 660mV Vhigh is the minimum when VDDIO is >= 1.05V +/-5%. If VDDIO is < 1.05V +/-5%, the minimum Vhigh will be VDDIOmin -

250mV. For example for VDDIO = 0.9V +/-5%, VHIGHmin will be 860mV - 250mV = 610mV.

Slew rate

Trf

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope

mV

Measurement on single ended signal using

absolute value. (Scope averaging off)

mV

1Guaranteed by design and characterization, not 100% tested in production. C

L = 2pF.

3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around

differential 0V.

4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on

the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations.

5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising

edge (i.e. Clock rising and Clock# falling).

6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross

absolute) allowed. The intent is to limit Vcross induced modulation by setting

Δ-Vcross to be smaller than Vcross absolute.

TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

IDDR

VDDR @100MHz

23

mA

IDDDIG

VDDIG, All outputs @100MHz

0.2

0.5

mA

IDDO

VDDO1.8, All outputs @100MHz

23

27

mA

IDDRPD

VDDR, CKPWRGD_PD# = 0

0.001

0.1

mA

2

IDDDIGPD

VDDDIG, CKPWRGD_PD# = 0

0.17

0.3

mA

2

IDDOPD

VDDO1.8, CKPWRGD_PD# = 0

0.4

0.8

mA

2

1 Guaranteed by design and characterization, not 100% tested in production.

2 Input clock stopped.

Operating Supply Current

Powerdown Current

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