Electronic Components Datasheet Search |
|
9DBV0441AKLFT Datasheet(PDF) 1 Page - Integrated Device Technology |
|
9DBV0441AKLFT Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 17 page DATASHEET 9DBV0441 REVISION E 04/28/16 1 ©2016 Integrated Device Technology, Inc. 4 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB w/Zo=100ohm 9DBV0441 Description The 9DBV0441 is a member of IDT's SOC-Friendly 1.8V Very-Low-Power (VLP) PCIe family. It has integrated output terminations providing Zo=100ohms for direct connection to 100ohm transmission lines. The device has 4 output enables for clock management, and 3 selectable SMBus addresses. Recommended Application 1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB) Output Features • 4 – 1-200Hz Low-Power (LP) HCSL DIF pairs w/ZO=100 Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps • DIF additive phase jitter is <100fs rms for PCIe Gen3 • DIF additive phase jitter <300fs rms for 12kHz-20MHz Features/Benefits • Direct connection to 100ohm transmission lines; saves 16 resistors compared to standard HCSL outputs • 53mW typical power consumption in PLL mode; minimal power consumption • Spread Spectrum (SS) compatible; allows use of SS for EMI reduction • OE# pins; support DIF power management • HCSL compatible differential input; can be driven by common clock sources • Programmable Slew rate for each output; allows tuning for various line lengths • Programmable output amplitude; allows tuning for various application environments • Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application • Outputs blocked until PLL is locked; clean system start-up • Software selectable 50MHz or 125MHz PLL operation; useful for Ethernet applications • Configuration can be accomplished with strapping pins; SMBus interface not required for device control • 3.3V tolerant SMBus interface works with legacy controllers • Space saving 32-pin 5x5mm VFQFPN; minimal board space • Selectable SMBus addresses; multiple devices can easily share an SMBus segment Block Diagram CONTROL LOGIC ^SADR_tri ^CKPWRGD_PD# ZDB PLL vOE(3:0)# ^vHIBW_BYPM_LOBW# CLK_IN# SDATA_3.3 SCLK_3.3 DIF2 DIF3 DIF1 DIF0 CLK_IN |
Similar Part No. - 9DBV0441AKLFT |
|
Similar Description - 9DBV0441AKLFT |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |