4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHM

4

REVISION E 04/28/16

9DBV0441 DATASHEET

Pin Descriptions

Pin#

Pin Name

Type

Pin Description

1

^vHIBW_BYPM_LOBW#

LATCHED IN

Trilevel input to select High BW, Bypass or Low BW mode.

See PLL Operating Mode Table for Details.

2

FB_DNC

DNC

True clock of differential feedback. The feedback output and feedback input are

connected internally on this pin. Do not connect anything to this pin.

3

FB_DNC#

DNC

Complement clock of differential feedback. The feedback output and feedback

input are connected internally on this pin. Do not connect anything to this pin.

4

VDDR1.8

PWR

1.8V power for differential input clock (receiver). This VDD should be treated as

an Analog power rail and filtered appropriately.

5

CLK_IN

IN

True Input for differential reference clock.

6

CLK_IN#

IN

Complementary Input for differential reference clock.

7

GNDR

GND

Analog Ground pin for the differential input (receiver)

8

GNDDIG

GND

Ground pin for digital circuitry

9

VDDDIG1.8

PWR

1.8V digital power (dirty power)

10

SCLK_3.3

IN

Clock pin of SMBus circuitry, 3.3V tolerant.

11

SDATA_3.3

I/O

Data pin for SMBus circuitry, 3.3V tolerant.

12

vOE0#

IN

Active low input for enabling DIF pair 0. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

13

DIF0

OUT

Differential true clock output

14

DIF0#

OUT

Differential Complementary clock output

15

GND

GND

Ground pin.

16

VDDO1.8

PWR

Power supply for outputs, nominally 1.8V.

17

vOE1#

IN

Active low input for enabling DIF pair 1. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

18

DIF1

OUT

Differential true clock output

19

DIF1#

OUT

Differential Complementary clock output

20

GNDA

GND

Ground pin for the PLL core.

21

VDDA1.8

PWR

1.8V power for the PLL core.

22

DIF2

OUT

Differential true clock output

23

DIF2#

OUT

Differential Complementary clock output

24

vOE2#

IN

Active low input for enabling DIF pair 2. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

25

VDDO1.8

PWR

Power supply for outputs, nominally 1.8V.

26

GND

GND

Ground pin.

27

DIF3

OUT

Differential true clock output

28

DIF3#

OUT

Differential Complementary clock output

29

vOE3#

IN

Active low input for enabling DIF pair 3. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

30

GND

GND

Ground pin.

31

^CKPWRGD_PD#

IN

Input notifies device to sample latched inputs and start up on first high assertion.

Low enters Power Down Mode, subsequent high assertions exit Power Down

Mode. This pin has internal pull-up resistor.

32

^SADR_tri

LATCHED IN Tri-level latch to select SMBus Address. See SMBus Address Selection Table.