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9DBV0441AKLF Datasheet(PDF) 7 Page - Integrated Device Technology |
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9DBV0441AKLF Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 17 page REVISION E 04/28/16 7 4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHM 9DBV0441 DATASHEET Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating Conditions TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES 1.8V Supply Voltage VDD Supply voltage for core, analog and LVCMOS outputs 1.7 1.8 1.9 V 1 TCOM Commmercial range 0 25 70 °C 1 TIND Industrial range -40 25 85 °C 1 Input High Voltage VIH Single-ended inputs, except SMBus 0.75 VDD VDD + 0.3 V 1 Input Mid Voltage VIM Single-ended tri-level inputs ('_tri' suffix) 0.4 VDD 0.6 VDD V1 Input Low Voltage VIL Single-ended inputs, except SMBus -0.3 0.25 VDD V1 IIN Single-ended inputs, VIN = GND, VIN = VDD -5 5 uA 1 IINP Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors -200 200 uA 1 Fibyp Bypass mode 1 200 MHz 2 Fipll100 100MHz PLL mode 50 100.00 140 MHz 2 Fipll125 125MHz PLL mode 62.5 125.00 175 MHz 2 Fipll62 50MHz PLL mode 25 50.00 65 MHz 2 Pin Inductance Lpin 7nH 1 CIN Logic Inputs, except DIF_IN 1.5 5 pF 1 CINDIF_IN DIF_IN differential clock inputs 1.5 2.7 pF 1,6 COUT Output pin capacitance 6 pF 1 Clk Stabilization TSTAB From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock 0.6 1 ms 1,2 Input SS Modulation Frequency fMODIN Allowable Frequency (Triangular Modulation) 30 31.500 33 kHz 1 OE# Latency tLATOE# DIF start after OE# assertion DIF stop after OE# deassertion 1 3 clocks 1,3 Tdrive_PD# tDRVPD DIF output enable after PD# de-assertion 300 us 1,3 Tfall tF Fall time of single-ended control inputs 5 ns 1,2 Trise tR Rise time of single-ended control inputs 5 ns 1,2 SMBus Input Low Voltage VILSMB VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V 0.8 V 1, 4 SMBus Input High Voltage VIHSMB VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V 2.1 3.6 V 1, 5 SMBus Output Low Voltage VOLSMB @ IPULLUP 0.4 V 1 SMBus Sink Current IPULLUP @ VOL 4mA 1 Nominal Bus Voltage VDDSMB 1.7 3.6 V 1 SCLK/SDATA Rise Time tRSMB (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 SCLK/SDATA Fall Time tFSMB (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 SMBus Operating Frequency fMAXSMB Maximum SMBus operating frequency 400 kHz 1,7 1Guaranteed by design and characterization, not 100% tested in production. 2Control input must be monotonic from 20% to 80% of input swing. 3Time from deassertion until outputs are >200 mV 6DIF_IN input 7The differential input clock must be running for the SMBus to be active 4 For V DDSMB < 3.3V, VILSMB <= 0.35VDDSMB 5 For V DDSMB < 3.3V, VIHSMB >= 0.65VDDSMB Ambient Operating Temperature Input Current Input Frequency Capacitance |
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