4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)

6

REVISION E 04/28/16

9DBV0431 DATASHEET

Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating

Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

1.8V Supply Voltage

VDD

Supply voltage for core, analog and LVCMOS

outputs

1.7

1.8

1.9

V

1

Commmercial range

0

25

70

°C

1

Industrial range

-40

25

85

°C

1

Input High Voltage

Single-ended inputs, except SMBus

V

1

Input Mid Voltage

Single-ended tri-level inputs ('_tri' suffix)

V1

Input Low Voltage

Single-ended inputs, except SMBus

-0.3

V1

-5

5

uA

1

Single-ended inputs

-200

200

uA

1

Bypass mode

1

200

MHz

2

100MHz PLL mode

50

100

140

MHz

2

125MHz PLL mode

62.5

125

175

MHz

2

50MHz PLL mode

25

50

65

MHz

2

Pin Inductance

7nH

1

Logic Inputs, except DIF_IN

1.5

5

pF

1

DIF_IN differential clock inputs

1.5

2.7

pF

1,6

Output pin capacitance

6

pF

1

Clk Stabilization

stabilization or de-assertion of PD# to 1st clock

0.6

1

ms

1,2

Input SS Modulation

Frequency

Allowable Frequency

(Triangular Modulation)

30

31.5

33

kHz

1

OE# Latency

DIF start after OE# assertion

DIF stop after OE# deassertion

1

3

clocks

1,3

Tdrive_PD#

DIF output enable after

PD# de-assertion

175

300

us

1,3

Tfall

Fall time of single-ended control inputs

5

ns

1,2

Trise

Rise time of single-ended control inputs

5

ns

1,2

SMBus Input Low Voltage

0.8

V

1,4

SMBus Input High Voltage

2.1

3.6

V

1,5

SMBus Output Low Voltage

0.4

V

1

SMBus Sink Current

4mA

1

Nominal Bus Voltage

1.7

3.6

V

1

SCLK/SDATA Rise Time

(Max VIL - 0.15) to (Min VIH + 0.15)

1000

ns

1

SCLK/SDATA Fall Time

(Min VIH + 0.15) to (Max VIL - 0.15)

300

ns

1

SMBus Operating Frequency

Maximum SMBus operating frequency

400

kHz

1,7

Ambient Operating

Temperature

Input Current

Input Frequency

Capacitance