2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER WITH ZO=100OHMS

2

REVISION F 04/28/16

9DBV0241 DATASHEET

Pin Configuration

Power Management Table

Power Connections

Frequency Select Table

PLL Operating Mode

SMBus Address

24 23 22 21 20 19

FB_DNC# 1

18 DIF1#

VDDR1.8 2

17 DIF1

CLK_IN 3

16 VDDA1.8

CLK_IN# 4

15 GNDA

GNDR 5

14 DIF0#

GNDDIG 6

13 DIF0

7

8

9 101112

24-pin VFQFPN, 4x4 mm, 0.5mm pitch

9DBV0241

epad is GND

^ prefix indicates internal 120KOhm pull up resistor

^v prefix indicates internal 120KOhm pull up AND pull

down resistor (biased to VDD/2)

v prefix indicates internal 120KOhm pull down resistor

True O/P

Comp. O/P

0

X

X

X

Low

Low

Off

1

Running

0

X

Low

Low

1

Running

1

0

Running

Running

1

Running

1

1

Low

Low

CLK_IN

OEx# Pin

PLL

DIFx

CKPWRGD_PD#

SMBus

OEx bit

1. If Bypass mode is selected, the PLL will be off, and outputs will be running.

VDD

GND

25

76

11,20

10,21

16

15

Input receiver analog

Digital Power

DIF outputs

PLL Analog

Description

Pin Number

FSEL

Byte3 [4:3]

CLK_IN

(MHz)

DIFx

(MHz)

00 (Default)

100.00

CLK_IN

01

50.00

CLK_IN

10

125.00

CLK_IN

11

Reserved

Reserved

HiBW_BypM_LoBW#

MODE

Byte1 [7:6]

Readback

Byte1 [4:3]

Control

0

PLL Lo BW

00

00

M

Bypass

01

01

1

PLL Hi BW

11

11

Address

1101101

x

+

Read/Write bit