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9DBV0231AKLFT Datasheet(PDF) 1 Page - Integrated Device Technology |
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9DBV0231AKLFT Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 17 page DATASHEET 9DBV0231 REVISION F 04/28/16 1 ©2016 Integrated Device Technology, Inc. 2-output 1.8V PCIe Gen1/2/3 Zero Delay / Fanout Buffer 9DBV0231 Description The 9DBV0231 is a member of IDT's 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 output enables for clock management. Recommended Application 1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer (ZDB/FOB) Output Features • 2 – 1-200MHz Low-Power (LP) HCSL DIF pairs Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps • DIF additive phase jitter is <100fs rms for PCIe Gen3 • DIF additive phase jitter <300fs rms (12k-20MHz) Features/Benefits • LP-HCSL outputs; save 4 resistors compared to standard HCSL outputs • 35mW typical power consumption in PLL mode; reduced thermal concerns • Spread Spectrum (SS) compatible; allows use of SS for EMI reduction • OE# pins; support DIF power management • HCSL compatible differential input; can be driven by common clock sources • SMBus-selectable features; optimize signal integrity to application • slew rate for each output • differential output amplitude • Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application • Outputs blocked until PLL is locked; clean system start-up • Device contains default configuration; SMBus interface not required for device control • 3.3V tolerant SMBus interface works with legacy controllers • Space saving 24-pin 4x4mm VFQFPN; minimal board space Block Diagram , CONTROL LOGIC ^vHIBW_BYPM_LOBW# ^CKPWRGD_PD# SDATA_3.3 SS- Compatible PLL vOE(1:0)# SCLK_3.3 CLK_IN CLK_IN# 2 DIF0 DIF1 |
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