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9DBV0231AKLF Datasheet(PDF) 8 Page - Integrated Device Technology

Part # 9DBV0231AKLF
Description  2-output 1.8V PCIe Gen1/2/3 Zero Delay /Fanout Buffer
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

9DBV0231AKLF Datasheet(HTML) 8 Page - Integrated Device Technology

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2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
8
REVISION F 04/28/16
9DBV0231 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
Electrical Characteristics–Phase Jitter Parameters
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
-3dB point in High BW Mode
2
2.7
4
MHz
1,5
-3dB point in Low BW Mode
1
1.4
2
MHz
1,5
PLL Jitter Peaking
tJPEAK
Peak Pass band Gain
1.05
2
dB
1
Duty Cycle
tDC
Measured differentially, PLL Mode
45
50
55
%
1
Duty Cycle Distortion
tDCD
Measured differentially, Bypass Mode @100MHz
-1
-0.1
1
%
1,3
tpdBYP
Bypass Mode, VT = 50%
2600
3370
4200
ps
1
tpdPLL
PLL Mode VT = 50%
0
112
200
ps
1,4
Skew, Output to Output
tsk3
VT = 50%
33
50
ps
1,4
PLL mode
13
50
ps
1,2
Additive Jitter in Bypass Mode
0.1
5
ps
1,2
1 Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4 All outputs at default slew rate
5 The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
PLL Bandwidth
BW
Skew, Input to Output
Jitter, Cycle to cycle
tjcyc-cyc
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
INDUSTRY
LIMIT
UNITS
Notes
tjphPCIeG1
PCIe Gen 1
32
52
86
ps (p-p) 1,2,3,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.8
1.4
3
ps
(rms)
1,2,3,5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
2.4
2.5
3.1
ps
(rms)
1,2,3,5
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
0.5
0.6
1
ps
(rms)
1,2,3,5
tjphSGMII
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
1.9
2
NA
ps
(rms)
1,6
tjphPCIeG1
PCIe Gen 1
0.1
5
N/A
ps (p-p) 1,2,3,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.2
0.3
N/A
ps
(rms)
1,2,3,4,
5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.00
0.1
N/A
ps
(rms)
1,2,3,4
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
0.00
0.1
N/A
ps
(rms)
1,2,3,4
tjphSGMII
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
165
200
N/A
ps
(rms)
1,6
tjphSGMII
125MHz, 12kHz to 20MHz, -20dB/decade rollover
< 1.5MHz, -40db/decade rolloff > 10MHz
251
300
N/A
ps
(rms)
1,6
1Guaranteed by design and characterization, not 100% tested in production.
4 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
5 Driven by 9FG432 or equivalent
6 Rohde&Schartz SMA100
Phase Jitter, PLL Mode
tjphPCIeG2
tjphPCIeG2
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
Additive Phase Jitter,
Bypass Mode


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