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9DBL0841BKILF Datasheet(PDF) 9 Page - Integrated Device Technology |
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9DBL0841BKILF Datasheet(HTML) 9 Page - Integrated Device Technology |
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9 / 19 page  REVISION D 08/16/16 9 8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER 9DBL08 DATASHEET Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Separate Reference Independent Spread (SRIS) Architectures5 Electrical Characteristics–Unfiltered Phase Jitter Parameters TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX INDUSTRY LIMIT UNITS Notes tjphPCIeG2-SRIS PCIe Gen 2 (PLL BW of 16MHz , CDR = 5MHz) 1.2 1.5 2 ps (rms) 1,2 tjphPCIeG3-SRIS PCIe Gen 3 (PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz) 0.5 ps (rms) 1,2,6 tjphPCIeG2-SRIS PCIe Gen 2 (PLL BW of 16MHz , CDR = 5MHz) 0.0 0.01 ps (rms) 1,2,4 tjphPCIeG3-SRIS PCIe Gen 3 (PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz) 0.0 0.01 ps (rms) 1,2,4,6 1 Applies to all outputs. Phase Jitter, PLL Mode n/a 6 This device does not support PCIe Gen3 SRIS in PLL mode. It supports PCIe Gen3 SRIS in bypass mode. Additive Phase Jitter, Bypass mode n/a 2 Based on PCIe Base Specification Rev3.1a. These filters are different than Common Clock filters. See http://www.pcisig.com for latest specifications. 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 For RMS values, additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2 ] where a is rms input jitter and c is rms total jitter. 5 As of PCIe Base Specification Rev4.0 draft 0.7, SRIS is not currently defined for Gen1 or Gen4. TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX INDUSTRY LIMIT UNITS Notes tjph156M 156.25MHz, 1.5MHz to 10MHz, -20dB/decade rollover < 1.5MHz, -40db/decade rolloff > 10MHz 159 N/A fs (rms) 1,2,3 tjph156M12k-20 156.25MHz, 12kHz to 20MHz, -20dB/decade rollover <12kHz, -40db/decade rolloff > 20MHz 363 N/A fs (rms) 1,2,3 1Guaranteed by design and characterization, not 100% tested in production. 3 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2] Additive Phase Jitter, Fanout Mode 2 DRiven by Rohde&Schartz SMA100 |
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