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LE25S161 Datasheet(PDF) 10 Page - ON Semiconductor |
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LE25S161 Datasheet(HTML) 10 Page - ON Semiconductor |
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10 / 54 page  LE25S161 www.onsemi.com 10 7. Device Operation 7-1. Standard SPI Modes The read, erase, program and other required functions of the device are executed through the command registers. The serial I/O corrugate is shown in "Figure 1. SPI Modes" and the command list are shown in "Table.1-1. Command Settings (Standard SPI)". At the falling CS edge the device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are normalized in 8 bit units and taken into the device interior in synchronization with the rising edge of SCK, which causes the device to execute operation according to the command that is input. The LE25S161 supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of SCK is high. Figure 1. SPI Modes 7-2. Dual SPI Modes The LE25S161 supports Dual SPI operations when using "Dual Output Read (RDDO: 3Bh)", "Dual I/O Read (RDIO: BBh)". The SI and SO pins change into the input/output pin (SIOx) during the Dual SPI modes. The command list is shown in "Table.1-2. Command Settings (Dual SPI)". Pin Configurations at Dual SPI Mode Standard SPI Dual SPI SI SIO0 SO SIO1 CS SCK SO SI High Impedance DATA DATA 1st byte 2nd byte 8CLK Mode0 Mode3 Nth byte MSB (Bit7) LSB (Bit0) |
Similar Part No. - LE25S161_16 |
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Similar Description - LE25S161_16 |
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