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MP7542TD Datasheet(PDF) 5 Page - Exar Corporation |
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MP7542TD Datasheet(HTML) 5 Page - Exar Corporation |
5 / 12 page MP7542 5 Rev. 2.00 Figure 1. Timing Diagram tAWS1 ADDRESS BUS VALID DATA BUS VALID tCWS1 tAWH tCWH tAWS2 tWR tCWS2 tDS tDH VINH VINL VINH VINL VINH VINL A0 - A1 CS WR DB3 - DB0 MP7542 Operation MP7542 Control Inputs A1 A0 CS WR XXX Resets DAC 12-bit register to code 0000 0000 0000 NOTES 1. 1 indicates logic HIGH 2. 0 indicates logic LOW 3. X indicates don’t care 4. indicates LOW to HIGH transition 5. MSB XXXX XXXX XXXX LSB 6. Although positive-going edge of either CS or WR will load data register, timing is optimized by using WR to latch data and using CS as a device enable. Table 1. Truth Table CLR X 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 1 0 0 0 0 0 X 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 No operation; device not selected Load LOW byte data register on edges as shown Load MIDDLE byte data register on edges as shown Load HIGH byte data register on edges as shown Load 12-bit DAC register with data in LOW byte, MIDDLE byte, & HIGH byte data registers Load applicable data register with data at D0 - D3 high byte middle byte low byte |
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