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CAV25M01 Datasheet(PDF) 9 Page - ON Semiconductor |
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CAV25M01 Datasheet(HTML) 9 Page - ON Semiconductor |
9 / 14 page CAV25M01 www.onsemi.com 9 Read Operations Read from Memory Array To read from memory, the host sends a READ instruction followed by a 24−bit address (see Table 11 for the number of significant address bits). After receiving the last address bit, the CAV25M01 will respond by shifting out data on the SO pin (as shown in Figure 9). Sequentially stored data can be read out by simply continuing to run the clock. The internal address pointer is automatically incremented to the next higher address as data is shifted out. After reaching the highest memory address, the address counter “rolls over” to the lowest memory address, and the read cycle can be continued indefinitely. The read operation is terminated by taking CS high. Read Identification Page Reading the additional 256−byte Identification Page (IP) is achieved using the same Read command sequence as used for Read from main memory array (Figure 9). The IPL bit from the Status Register must be set (IPL = 1) before attempting to read from the IP. The [A7:A0] are the address significant bits that point to the data byte shifted out on the SO pin. If the CS continues to be held low, the internal address register defined by [A7:A0] bits is automatically incremented and the next data byte from the IP is shifted out. The byte address must not exceed the 256−byte page boundary. Read Status Register To read the status register, the host simply sends a RDSR command. After receiving the last bit of the command, the CAV25M01 will shift out the contents of the status register on the SO pin (Figure 10). The status register may be read at any time, including during an internal write cycle. SCK SI SO 0 000 00 11 BYTE ADDRESS* 0 1 2 3 4 5 6 7 8 9 10 2829 30 31 323334 353637 38 7 6 5 4 3 2 1 0 DATA OUT MSB HIGH IMPEDANCE OPCODE Figure 9. READ Timing Note: Dashed Line = mode (1, 1) * Please check the Byte Address Table (Table 11). CS AN A0 01 2 3 4 5 6 7 8 10 911 12 13 14 SCK SI DATA OUT MSB HIGH IMPEDANCE OPCODE SO 7 6 5 4 3 2 1 0 00 0 0 0 101 Note: Dashed Line = mode (1, 1) Figure 10. RDSR Timing CS |
Similar Part No. - CAV25M01_15 |
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Similar Description - CAV25M01_15 |
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