11/23

BD63620AEFV

TSZ02201-0P2P0B700670-1-2

© 2014 ROHM Co., Ltd. All rights reserved.

11.Mar.2014 Rev.001

www.rohm.com

TSZ22111・15・001

●Translator circuit

This series builds in translator circuit and can drive stepping motor in CLK-IN mode.

The operation of the translator circuit in CLK-IN drive mode is described as below.

○Reset operation

The translator circuit is initialized by power ON Reset function and PS terminal.

・Initializing operation when power supply is turned on

①If power supply is turned on at PS=L (Please use this sequence as a general rule)

When power supply is turned on, the power ON reset function operates in IC and initialized, but as long as it is PS=L,

the motor output is the OPEN state. After power supply is turned on, because of the changing of PS=L⇒H, the motor

output becomes the ACTIVE state, and the excitation is started at the initial electrical angle.

But at the time of PS=L⇒H, it returns from the standby state to the normal state and there is a delay of 40μs(max.)

until the motor output has become the ACTIVE state.

②If power supply is turned on at PS=H

When power supply is turned on, the power ON function in IC operates, and initialized before the motor output

becomes the ACTIVE state, and the excitation is started at the initial electrical angle.

・Initializing operation during motor operating

Please input the reset signal to PS terminal when the translator circuit is initialized during motor operating. (Refer to

P.14) But at the time of PS=L⇒H, it returns from the standby state to the normal state and there is a delay of 40μs

(max.) until the motor output has become the ACTIVE state, so please be careful.

○Control input timing

Please input as shown below because the translator circuit operates at the rising edge of CLK signal. If you disobey this

timing and input, then there is the possibility that the translator circuit does not operate as expected. In addition, at the time

of PS=L⇒H, it returns from the standby state to the normal state and there is a delay of 40μs (max.) until the motor output

has become the ACTIVE state, so within this delay interval there is no phase advance operation even if CLK is inputted.

A:PS minimum input pulse width･･････20

μs

B:PS rising edge～CLK rising edge input possible maximum delay time･･････40

μs

C:CLK minimum period･･････4

μs

D:CLK minimum input H pulse width･･････2

μs

E:CLK minimum input L pulse width･･････2

μs

F:MODE0,MODE1,CW_CCW set-up time･･････1

μs

G:MODE0,MODE1,CW_CCW hold time･･････1

μs

Reset is released

ACTIVE

Motor output OPEN

Motor output ON

②

PS

CLK

OUT1A

OUT1B

Delay

①

PS

CLK

MODE0

F

G

F

G

MODE1

CW_CCW

A

D

E

B

C