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TSZ02201-0P2P0B301460-1-2

© 2016 ROHM Co., Ltd. All rights reserved.

21.Jun.2016 Rev.001

www.rohm.com

TSZ22111・15・001

BD62220AEFV

(8) RNF1S,RNF2S/ Input Terminal of Current Limit Comparator

In this series, RNFS terminal, which is the input terminal of current limit comparator, is independently arranged in

order to decrease the lowering of current-detection accuracy caused by the wire impedance inside the IC of RNF

terminal. Therefore, please make sure to connect RNF terminal and RNFS terminal together when using PWM

constant current control. In addition, in case of interconnection, the lowering of current-detection accuracy caused by

the impedance of board pattern between RNF terminal and the current-detecting resistor can be decreased because

the wires from RNFS terminal is connected near the current-detecting resistor. Moreover, please design the pattern in

such a way that there is no noise spike.

(9) VREF1,VREF2/ Output Current Value-setting Terminal

This is the terminal to set the output current value for PWM constant current control or motor locking.

The output current value can be set by VREF voltage and current-detecting resistor (RNF resistor).

[ ]

)

{

}

[ ]

Ω

=

RNF

/

IC

inside

ratio

division

8

/

V

VREF

A

IOUT

current

Output

Please avoid using it with VREF terminal open. If VREF terminal is open, there is possibility of malfunctions as the

setting current increases and a large current flows etc. This is caused by unstable input and increasing VREF voltage.

Please take note of the input voltage range because if voltage of over 2V is applied on VREF terminal, there is also a

danger that large current flows in the output and OCP or TSD will operate. Also, when selecting the resistance value

please take into consideration the outflow current (max 2μA) produced by resistance division. The minimum current,

which can be controlled by VREF voltage, is determined by motor coil’s L & R values and minimum ON time. There is

a minimum ON time in PWM drive.

(10) CR/ Connection terminal of CR for Setting Switching Frequency

This is the terminal to set the switching frequency of the output. Please connect the external C (330pF to 680pF) and

R (10k

Ω to 150kΩ) between this terminal and GND. Please refer to page 8.

Please connect the external components to GND in such a way that the interconnection does not have impedance in

common with other GND patterns. In addition, please create the pattern design in such a way to keep such sudden

pulses as square wave etc. away and that there is no noise spike. Please mount the two components of C and R if

PWM constant current control is being used. This is because normal PWM constant current control cannot be used if

CR terminal is open or it is biased externally. When not using PWM constant current control, connect this terminal to

GND.

(11) FAILA/ Fault Signal Output Terminal

FAILA outputs low signal when Over-Current Protection (OCP) or Thermal Shutdown (TSD) operates.

Even if Under Voltage Lock Out (UVLO) or Over Voltage Lock Out (OVLO) operates, FAILA signal doesn’t turn low

(i.e. high).

This terminal is an open drain type, so please set the pull up resistor (5k

Ω to 100kΩ) to power supply less than 7V

(i.e. 5V or 3.3V). If not using this terminal, please connect it to GND.

OCP

TSD

FAILA

OFF

OFF

H (OFF)

OFF

ON

M (ON)

ON

OFF

L (ON)

ON

ON

L (ON)

(12) NC Terminal

This terminal is unconnected electrically with IC internal circuit.

(13) IC Back Metal

For HTSSOP-B28 package, the metal heat sink is mounted on IC’s back side. It becomes a prerequisite to use this

metal as heat sink so please secure the heat sink area sufficiently by soldering it to the GND plane on the board. Get

as wide GND pattern as possible. Please be careful because the allowable power dissipation as shown in page 14

cannot be attained if the metal heat sink is not connected by solder. Moreover, the back side metal is shorted with IC

chip’s back side and it becomes the GND potential, so there is adanger of malfunction and destruction if it is shorted

with potentials other than GND. Therefore; please do not design patterns other than GND through the IC’s back side.