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MAX1304 Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX1304 Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 36 page 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges 6 _______________________________________________________________________________________ Note 1: For the MAX1304/MAX1305/MAX1306, VIN = 0 to +5V. For the MAX1308/MAX1309/MAX1310, VIN = -5V to +5V. For the MAX1312/MAX1313/MAX1314, VIN = -10V to +10V. Note 2: All channel performance is guaranteed by correlation to a single channel test. Note 3: The analog input resistance is terminated to an internal bias point (Figure 5). Calculate the analog input current using: for VCH within the input voltage range. Note 4: Throughput rate is given per channel. Throughput rate is a function of clock frequency (fCLK). The external clock through- put rate is specified with fCLK = 16.67MHz and the internal clock throughput rate is specified with fCLK = 15MHz. See the Data Throughput section for more information. Note 5: The REF input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF input current using: for VREF within the input voltage range. Note 6: The REFMS input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REFMS input current using: for VREFMS within the input voltage range. Note 7: All analog inputs are driven with a -0.4dBFS 500kHz sine wave. Note 8: Shutdown current is measured with the analog input floating. The large amplitude of the maximum shutdown current speci- fication is due to automated test equipment limitations. Note 9: CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor droop. Note 10: CS to WR and CS to RD are internally AND together. Setup and hold times do not apply. Note 11: Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST and the falling edge of EOLC to a maximum of 1ms. I VV R REFMS REFMS REFMS = − 25 . I VV R REF REF REF = − 25 . I VV R CH CH BIAS CH _ _ _ = − PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input-Data Setup Time tDTW Figure 6 10 ns Input-Data Hold Time tWTD Figure 6 10 ns External CLK Period tCLK Figures 8, 9 0.05 10.00 µs External CLK High Period tCLKH Logic sensitive to rising edges, Figures 8, 9 20 ns External CLK Low Period tCLKL Logic sensitive to rising edges, Figures 8, 9 20 ns External Clock Frequency fCLK (Note 11) 0.1 20 MHz Internal Clock Frequency fINT 15 MHz CONVST High to CLK Edge tCNTC Figures 8, 9 20 ns ELECTRICAL CHARACTERISTICS (continued) (AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo- lar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.) |
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Similar Description - MAX1304 |
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