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Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.

Features

•

Conforms to EBU specification for DVB-S and

DirecTV specification for DSS

•

On-chip digital filtering supports 1 - 45 MSps

symbol rates

•

On-chip 60 or 90 MHz dual-ADC

•

High speed scanning mode for blind symbol

rate/code rate acquisition

•

Automatic spectral inversion resolution

•

High level software interface for minimum

development time

•

Up to ±22 MHz LNB frequency tracking

•

DiSEqC™ v2.2: receive/transmit for full control of

LNB, dish and other components

•

Compact 64 pin LQFP package (7 x 7 mm)

•

Sleep pin gives ~1,000 fold reduction in power to

requirements

Applications

•

DVB 1 - 45 MSps compliant satellite receiver

•

DSS 20 MSps compliant satellite receivers

•

SMATV trans-modulators. (Single Master

Antenna TV)

•

Satellite PC applications

Description

The

ZL10312

is

a

QPSK/BPSK

1 - 45 MSps

demodulator and channel decoder for digital satellite

television transmissions to the European Broadcast

Union ETS 300 421 specification. It receives analogue

I and Q signals from the tuner, digitises and digitally

demodulates this signal, and implements the complete

DVB/DSS FEC (Forward Error Correction), and de-

scrambling function. The output is in the form of

MPEG2 or DSS transport stream data packets. The

ZL10312 also provides automatic gain control to the RF

front-end device.

The ZL10312 has a serial 2-wire bus interface to the

control microprocessor. Minimal software is required to

control the ZL10312 because of the built in automatic

search and decode control functions.

November 2004

Ordering Information

ZL10312QCG

64 Pin LQFP

Trays, Bake & Drypack

ZL10312QCF

64 Pin LQFP

Tape & Reel

ZL10312QCG1

64 Pin LQFP*

Trays, Bake & Drypack

ZL10312UBH

Die supplied in wafer form**

*Pb Free Matte Tin

0

°C to +70°C

ZL10312

Satellite Demodulator

Data Sheet

Figure 1 - Functional Block Diagram

I I/P

Q I/P

Dual ADC

De-rotator

Decimation

Filtering

Timing recovery

Matched filter

Phase recovery

MPEG/

DSS

Packets

Bus I/O

2-Wire Bus

Interface

Acquisition

Control

Clock Generation

Analog

AGC

Control

DVB

DSS

FEC