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XR16C850CJ Datasheet(PDF) 7 Page - Exar Corporation

Part # XR16C850CJ
Description  UART with 128-byte FIFO?셲 FIFO Counters and Half-duplex Control
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XR16C850CJ Datasheet(HTML) 7 Page - Exar Corporation

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XR16C850
7
Rev. 1.20
is framing error bit and D12 is the break bit.
BUS8/16
-
-
25
28
I
8 or 16 Bit Bus select (internal pull-up). For normal
8 bit data bus operation this pin should be connected
to VCC. Connect this pin to GND for 16 bit data bus
operation where RX data errors (parity, framing and
break) are presented on the data bus as D10, D11
and D12 along with the data byte.
CLK8/16
-
-
-
27
I
Transmit / Receive data sampling clock rate (inter-
nal pull-up). For normal operation this pin should be
connected to VCC for 16X sampling clock (stan-
dard). Connect to GND for 8X sampling to double the
data rates.
DRQ
-
-
-
32
O
Receive DMA Request. A Receive ready request is
generated by bringing a RxDRQ line to a high level.
DRQ line is held high until the corresponding DMA
acknowledge (-DACK) line goes low.
-DACK
-
-
-
46
I
DMA Acknowledge Bit (internal pull-up). DMA cycle
will start processing when CPU/Host sets this input
to low. Connect this pin to VCC when not used.
-DDIS
(See LPT-2)
GND
20
22
18
19
Pwr
Signal and Power Ground.
INT
(See IRQA)
-IOR
21
24
19
21
I
Input/Output Read (active low strobe). A logic 0 on
this pin transfers the contents of the 850 data bus to
the CPU. Connect this pin to VCC when IOR is used.
-IOW
18
20
16
17
I
Input/Output Write (active low strobe) - A logic 0 on
this pin transfers the contents of the CPU data bus
to the addressed internal register. Connect this pin
to VCC when IOW is used.
IRQA / INT
30
33
30
33
O
Interrupt Request “A” or Interrupt (three state, open
source, active high) - During PC mode of operation,
this pin functions as IRQA. IRQA is enabled when
Symbol
Pin
Signal
Pin Description
40
44
48
52
type
SYMBOL DESCRIPTION


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