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CS8420 Datasheet(PDF) 3 Page - Cirrus Logic |
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CS8420 Datasheet(HTML) 3 Page - Cirrus Logic |
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3 / 80 page  CS8420 DS245PP2 3 12.3 Power Supply, Grounding, and PCB layout ................................................................... 44 12.4 Synchronization of Multiple CS8420s ............................................................................ 45 12.5 Extended Range Sample Rate Conversion ................................................................... 45 13. SOFTWARE MODE - PIN DESCRIPTION ........................................................................... 46 14. HARDWARE MODES ........................................................................................................... 49 14.1 Overall Description ........................................................................................................ 49 14.1.1 Hardware Mode Definitions ............................................................................... 49 14.1.2 Serial Audio Port Formats ................................................................................. 49 14.2 Hardware Mode 1 Description ....................................................................................... 50 14.2.1 Pin Description - Hardware Mode 1 .................................................................. 51 14.3 Hardware Mode 2 Description ...................................................................................... 53 14.3.1 Pin Description - Hardware Mode 2 .................................................................. 54 14.4 Hardware Mode 3 Description ....................................................................................... 56 14.4.1 Pin Description - Hardware Mode 3 .................................................................. 58 14.5 Hardware Mode 4 Description ....................................................................................... 60 14.5.1 Pin Description - Hardware Mode 4 .................................................................. 62 14.6 Hardware Mode 5 Description ....................................................................................... 64 14.6.1 Pin Description - Hardware Mode 5 .................................................................. 65 14.7 Hardware Mode 6 Description ....................................................................................... 67 14.7.1 Pin Description - Hardware Mode 6 .................................................................. 68 15. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER COMPONENTS .............................................................. 70 15.1 AES3 Transmitter External Components ....................................................................... 70 15.2 AES3 Receiver External Components ........................................................................... 70 15.3 Isolating Transformer Requirements ............................................................................. 71 16. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT .......... 72 16.1 AES3 Channel Status(C) Bit Management .................................................................... 72 16.1.1 Manually accessing the E buffer ....................................................................... 72 16.1.2 Reserving the first 5 bytes in the E buffer ......................................................... 74 16.1.3 Serial Copy Management System (SCMS) ....................................................... 74 16.1.4 Channel Status Data E Buffer Access .............................................................. 74 16.1.5 One Byte mode ................................................................................................. 74 16.1.6 Two Byte mode ................................................................................................. 74 16.2 AES3 User (U) Bit Management .................................................................................... 75 16.2.1 Mode 1: Transmit All Zeros ............................................................................... 75 16.2.2 Mode 2: Block Mode ......................................................................................... 75 16.2.3 IEC60958 Recommended U Data Format For Consumer Applications ............ 75 16.2.4 Mode (3): Reserved .......................................................................................... 76 16.2.5 Mode (4): IEC Consumer B ............................................................................... 76 17. PARAMETER DEFINITIONS ................................................................................................ 77 18. PACKAGE DIMENSIONS .................................................................................................... 78 LIST OF FIGURES Figure 1. Audio Ports Master Mode Timing..................................................................................... 7 Figure 2. Audio Ports Slave Mode and Data I/O Timing ................................................................. 7 Figure 3. SPI Mode Timing ............................................................................................................. 8 Figure 4. I2C Mode Timing .............................................................................................................. 9 Figure 5. Recommended Connection Diagram for Software Mode .............................................. 10 Figure 6. Software Mode Audio Data Flow Switching Options...................................................... 12 Figure 7. Serial Audio Input, using PLL, SRC enabled ................................................................. 13 Figure 8. Serial Audio Input, No PLL, SRC enabled ..................................................................... 13 Figure 9. AES3 Input, SRC enabled ............................................................................................. 13 Figure 10. Serial Audio Input, AES3 Input Clock Source, SRC Enabled ...................................... 13 |
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