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DSC400-2433Q0001KI1T Datasheet(PDF) 7 Page - Micrel Semiconductor |
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DSC400-2433Q0001KI1T Datasheet(HTML) 7 Page - Micrel Semiconductor |
7 / 15 page ______________________________________________________________________________________________________________________________________________ DSC400 Page 7 DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator LVDS: Typical Termination Scheme If the 100Ω clamping resistor does not exist inside the receiving device, it should be added externally on the PCB and placed as close as possible to the receiver. LVDS Outputs Output offset Voltage VOS R=100Ω Differential 1.125 1.4 V Delta Offset Voltage ∆VOS 50 mV Pk to Pk Output Swing VPP Single-Ended 350 mV Output Transition time3 Rise Time Fall Time tR tF 20% to 80% RL=50Ω, CL= 2pF 200 ps Frequency f0 Single Frequency 2.3 460 MHz Output Duty Cycle SYM Differential 48 52 % Supply Current – IO2 IDDio Per output at 125MHz 9 12 mA Period Jitter JPER 2.5 psRMS Integrated Phase Noise JPH 200kHz to 20MHz @156.25MHz 100kHz to 20MHz @156.25MHz 12kHz to 20MHz @156.25MHz 0.28 0.4 1.7 2 psRMS |
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