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Table 2. R8292 68-Pin PLCC Pin Signal Descriptions

Signal Name

Type

Description

ALE

O

Address Latch Enable. ALE signals the start of an external bus cycle and indicates that valid address

information is available on lines A15:8 and AD7:0. An external latch can use ALE to demultiplex the address

from the address/data bus.

AVCC

PWR

Analog VCC. AVCC input for the phase locked loop circuitry.

DM0, DP0

I/O

USB Port 0. DP0 and DM0 are the differential data plus and data minus signals of USB port 0, the upstream

differential port. These lines do not have internal pullup resistors. Provide an external 1.5 K

at DP0. If DP0 is not pulled high, a continuous SEO (USB reset) will be applied to these inputs causing the

8x931 to stay in reset.

EA#

I

External Access. Directs program memory accesses to on-chip or off-chip code memory. For EA# strapped

to ground, all program memory accesses are off-chip. For EA# strapped to VCC , program accesses on-chip

ROM if the address is within the range of the on-chip ROM; otherwise the access is off-chip. The value of

EA# is latched at reset. For devices without on-chip ROM, EA# must be strapped to ground.

ECAP

I

External Capacitor. Connect a 2.2 µF capacitor between this pin and VSS to ensure proper operation of the

differential line drivers.

FSSEL

I

Full Speed Select. Connect to VCC for 12MHz Xtal and 12Mbps full speed USB rate.

INT1#

I

HINT. Host bus interrupt input is set high by MCU when the MCU receiver error flag, received data available,

transmitter holding register empty, or modem status interrupt is asserted.

INT0#

I

RINGWAKE. Used to notify the host of an incoming ring in order to come out of suspend mode.

LED3:0

O

LED Drivers. Designed to drive LEDs connected directly to VCC. NC.

OVRI#/P3.0

I

Overcurrent Sense. Sense input to indicate an overcurrent condition on an external down-stream port.

Active low with an internal pullup. NC.

P0.7:0

I/O

Address/Data Lines. Eight-bit, open-drain, bidirectional I/O lines with Schmitt trigger inputs that represent

lower byte of external memory address multiplexed with data.

P1.7

I/O

NC. Quasi-bidirectional I/O port with internal pullup.

P1.6

O

Ready Indicate. Active low output to drive READY LED. Port has internal pullup.

P1.5

O

DCD Indicate. Active low output to drive DCD LED. Port has internal pullup.

P1.4

O

DATA Indicate. Active low output to drive DATA LED. Port has internal pullup.

P1.3

O

MODEMPWRCNTRL. Active low output used to control power supply to non-USB side of isolation. Port has

internal pullup.

P1.2

O

MDMRESET. Active low output used to reset the MCU and MDP. This port has an internal pullup.

P1.1

I/O

NC. Quasi-bidirectional I/O port with internal pullup.

P1.0

I/O

NC. Quasi-bidirectional I/O port with internal pullup.

P2.7:0

O

Address Lines. Eight-bit port with internal pullups used for upper byte of external memory address.

P3.5

I/O

NC. Quasi-bidirectional I/O port with internal pullup.

P3.4

I/O

NC. Quasi-bidirectional I/O port with internal pullup.

PLLSEL

I

Phase-locked Loop Select. Connect to VCC for 12MHz Xtal and 12Mbps full speed USB rate.

PSEN#

O

Program Store Enable. Read signal output. Asserted for read accesses to external program memory.

RD#

O

Read. Asserted for read accesses to external data memory.

RST

I

Reset. Reset input to the chip. Holding this pin high for 64 oscillator periods while the oscillator is running

resets the device. The port pins are driven to their reset conditions when a voltage greater than VIH1 is

applied, whether or not the oscillator is running. This pin has an internal pulldown resistor which allows the

device to be reset by connecting a capacitor between this pin and VCC.

Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation.

SOF#/P3.1

O

Start of Frame. Start of frame pulse. Active low. Asserted for 8 states when frame timer is locked to USB

frame timing and SOF token or artificial SOF is detected. NC.