P3P623S05A/B, P3P623S09A/B

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3

Figure 3. Pin Configuration for P3P623S09A/B

1

2

3

413

14

15

16

CLKA4

CLKA3

CLKOUT

VDD

CLKIN

CLKA1

CLKA2

VDD

5

6

7

89

10

11

12

P3P623S09A/B

CLKB4

CLKB3

GND

S1

GND

CLKB1

CLKB2

S2

Table 2. PIN DESCRIPTION FOR P3P623S05A/B

Pin #

Pin Name

Type

Description

1

CLKIN (Note 1)

I

External reference Clock input, 5 V tolerant input.

2

CLKA1 (Note 2)

O

Buffered clock Bank A output (Note 4)

3

CLKA2 (Note 2)

O

Buffered clock Bank A output (Note 4)

4

VDD

P

3.3 V supply

5

GND

P

Ground

6

CLKB1 (Note 2)

O

Buffered clock Bank B output (Note 4)

7

CLKB2 (Note 2)

O

Buffered clock Bank B output (Note 4)

8

S2 (Note 3)

I

Select input, bit 2. See Select Input Decoding table for P3P623S09A/B for more details.

9

S1 (Note 3)

I

Select input, bit 1. See Select Input Decoding table for P3P623S09A/B for more details.

10

CLKB3 (Note 2)

O

Buffered clock Bank B output (Note 4)

11

CLKB4 (Note 2)

O

Buffered clock Bank B output (Note 4)

12

GND

P

Ground

13

VDD

P

3.3 V supply

14

CLKA3 (Note 2)

O

Buffered clock Bank A output (Note 4)

15

CLKA4 (Note 2)

O

Buffered clock Bank A output (Note 4)

16

CLKOUT (Note 2)

O

Buffered clock output. Internal feedback on this pin.

1. Weak pull−down

2. Weak pull−down on all outputs

3. Weak pull−up on these inputs

4. Buffered clock output is Timing−Safe

Table 3. SELECT INPUT DECODING TABLE FOR P3P623S09A/B

S2

S1

CLK A1 − A4

CLK B1 − B4

CLKOUT (Note 5)

Output Source

PLL Shut−Down

0

0

Three−state

Three−state

Driven

PLL

N

0

1

Driven

Three−state

Driven

PLL

N

1

0

Driven

Driven

Driven

Reference

Y

1

1

Driven

Driven

Driven

PLL

N

5. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the

reference and the Output.