NB2309A

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2

CLKOUT

CLKA1

CLKA2

CLKA3

CLKA4

PLL

MUX

CLKB1

CLKB2

CLKB3

CLKB4

SELECT INPUT

DECODING

Figure 1. Block Diagram

REF

S2

S1

Table 1. SELECT INPUT DECODING

S2

S1

Clock A1 − A4

Clock B1 − B4

CLKOUT

(Note 1)

Output Source

PLL

ShutDown

0

0

Three−state

Three−state

Driven

PLL

N

0

1

Driven

Three−state

Driven

PLL

N

1

0

Driven

Driven

Driven

Reference

Y

1

1

Driven

Driven

Driven

PLL

N

1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the

reference and the output.