BD3531F

11/15

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TSZ22111・15・001

TSZ02201-0J2J0A900950-1-2

02.Nov.2015 Rev.001

Operational Notes

– continued

12.

Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should

be avoided.

Figure 13. Example of monolithic IC structure

13.

Thermal Shutdown Circuit(TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always

be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction

temperature (Tj) will exceed 175°C which will activate the TSD circuit that will turn OFF all output pins. When the Tj

falls below the TSD threshold, the circuits are automatically restored to normal operation.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from

heat damage.

14. Capacitor Across Output and GND

If a large capacitor is connected between the output pin and ground pin, current from the charged capacitor can flow

into the output pin and may destroy the IC when the VCC or IN pin is shorted to ground or pulled down to 0V. Use a

capacitor smaller than 1000µF between output and ground.

15. Output Capacitor

Do not fail to connect a output capacitor and resister to VREF output terminal for stabilization of output voltage. The

capacitor connected to VREF output terminal works as a loop gain phase compensator. Insufficient capacitance and

resister may cause an oscillation. It is recommended to use a low temperature coefficient 2.2

μF ceramic capacitor and

0.5Ω resister though it depends on ambient temperature and load conditions. It is therefore requested to carefully

check under the actual temperature and load conditions to be applied.

16. Output Capacitor

Do not fail to connect a capacitor to VTT output pin for stabilization of output voltage. This output capacitor works as a

loop gain phase compensator and an output voltage variation reducer in the event of sudden change in load.

Insufficient capacitance may cause an oscillation. And if the equivalent series resistance (ESR) of this capacitor is high,

the variation in output voltage increases in the event of sudden change in load. It is recommended to use a 220

μF

functional polymer capacitor, though it depends on ambient temperature and load conditions. Using a low ESR ceramic

capacitor may reduce a loop gain phase margin and cause an oscillation, which may be improved by connecting a

resistor in series with the capacitor. It is therefore requested to carefully check under the actual temperature and load

conditions to be applied.

N

N

P

+

P

N

N

P

+

P Substrate

GND

N

P

+

N

N

P

+

N P

P Substrate

GND

GND

Parasitic

Elements

Pin A

Pin A

Pin B

Pin B

B

C

E

Parasitic

Elements

GND

Parasitic

Elements

C

B

E

Transistor (NPN)

Resistor

N Region

close-by

Parasitic

Elements