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8V49NS0312NLGI8 Datasheet(PDF) 11 Page - Integrated Device Technology |
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8V49NS0312NLGI8 Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 57 page 11 ©2016 Integrated Device Technology, Inc. September 2, 2016 8V49NS0312 Datasheet Fractional Output Divider (Bank D) For the fractional output divider in Bank D, the output divide ratio is given by: Where, ▪ FINT = Integer Part: 5, 6, ...(24-1) - given by ND_FINT[3:0] ▪ FRAC = Fractional Part: 0, 1, 2, ...(224-1)- given by ND_FRAC[23:0] ▪ FDIV = post-divider: 1, 2 or 4- given by ND_DIVF[1:0] This provides a frequency range of 20MHz to 312.5MHz. Output Drivers Each of the four output banks are provided with pin or register-controlled output drivers. Differential outputs may be individually selected as LVDS, LVPECL or POWER-DOWN. When powered down, both outputs of the differential output pair will drive a logic-high level, and the single-ended QD1output will be in Hi-Z state. The differential outputs may individually choose one of several different output voltage swings: 350mV, 500mV or 750mV, measured single-ended. Note that under pin-control, all differential outputs within an output bank will assume the same configuration. Pin-control does not allow configuration of individual outputs within a bank. Pin Control of the Output Frequencies and Protocols See Table 8, Table 9, Table 10, Table 11 and Table 12, for pin-control settings. All of the output frequencies assume fVCO = 2500MHz. With different fVCO configurations, the pins may still be used to select the indicated divide ratios for each bank, but the fOUT will be different. Note that the control pins do not affect the internal register values, but act directly on the output structures. So register values will not change to match the control input pin selections. Each output bank may be powered-up / down and enabled / disabled by register bits. In the disabled state, an output will drive a logic low level. The default state is all outputs enabled. Pin-control does not require register access to enable the outputs. Additionally, individual outputs within a bank may be powered up / down. Table 8: Definition of Output Disabled / Power-down OUTPUT CONDITION QMNa a. QMN refers to output pins QA[0:3], QB[0:3], QC[0:1] and QD0. nQMNb b. nQMN refers to output pins nQA[0:3], nQB[0:3], nQC[0:1] and nQD0. QD1 DISABLED (register-control only) LOW HIGH LOW POWER-DOWN (pin-control or register-control) HIGH HIGH Hi-Z fOUT fVCO 2FINT FRAC 2 24 ---------------- + FDIV ------------------------------------------------------------------------------ = |
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