© Semiconductor Components Industries, LLC, 2012

March, 2012 − Rev. 4

1

Publication Order Number:

NB6L295/D

NB6L295

2.5V / 3.3V Dual Channel

Programmable Clock/Data

Delay with Differential

LVPECL Outputs

Multi−Level Inputs w/ Internal Termination

The NB6L295 is a Dual Channel Programmable Delay Chip

designed primarily for Clock or Data de−skewing and timing

adjustment. The NB6L295 is versatile in that two individual variable

delay channels, PD0 and PD1, can be configured in one of two

operating modes, a Dual Delay or an Extended Delay.

In the Dual Delay Mode, each channel has a programmable delay

section which is designed using a matrix of gates and a chain of

multiplexers. There is a fixed minimum delay of 3.2 ns per channel.

The Extended Delay Mode amounts to the additive delay of PD0

plus PD1 and is accomplished with the Serial Data Interface MSEL bit

set High. This will internally cascade the output of PD0 into the input

of PD1. Therefore, the Extended Delay path starts at the IN0/IN0

inputs, flows through PD0, cascades to the PD1 and outputs through

Q1/Q1. There is a fixed minimum delay of 6 ns for the Extended

Delay Mode.

The required delay is accomplished by programming each delay

channel via a 3−pin Serial Data Interface, described in the application

section. The digitally selectable delay has an increment resolution of

typically 11 ps with a net programmable delay range of either 0 ns to

6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the

Extended Delay Mode.

The Multi−Level Inputs can be driven directly by differential

LVPECL, LVDS or CML logic levels; or by single ended LVPECL,

LVCMOS or LVTTL. A single enable pin is available to control both

inputs. The SDI input pins are controlled by LVCMOS or LVTTL

level signals. The NB6L295 LVPECL output contains temperature

compensation circuitry. This device is offered in a 4 mm x 4 mm

24−pin QFN Pb−free package. The NB6L295 is a member of the

ECLinPS MAX

™ family of high performance products.

Features

Channel

Extended Delay Mode

Mode

Compatible

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

MARKING

DIAGRAM*

http://onsemi.com

QFN−24

MN SUFFIX

CASE 485L

A

= Assembly Location

L

= Wafer Lot

Y

= Year

W

= Work Week

G

= Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

See detailed ordering and shipping information in the package

dimensions section on page 12 of this data sheet.

ORDERING INFORMATION

NB6L

295

ALYWG

G

1

24

24

1