NB3W1900L

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10

Table 14. ELECTRICAL CHARACTERISTICS − PHASE JITTER PARAMETERS

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Phase Jitter, PLL Mode

PCIe Gen 1 (Notes 32 and 33)

86

ps (p−p)

PCIe Gen 2 Lo Band 10 kHz < f < 1.5 MHz (Note 32)

3

ps (rms)

PCIe Gen 2 High Band 1.5 MHz < f < Nyquist (50 MHz)

(Note 32)

3.1

ps (rms)

PCIe Gen 3

(PLL BW of 2−4 MHz, CDR = 10 MHz)

(Notes 32, 33 and 34)

1

ps (rms)

QPI & SMI

(100.00 MHz or 133.33 MHz, 4.8 Gb/s, 6.4 Gb/s 12UI)

(Note 35)

0.5

ps (rms)

QPI & SMI (100.00 MHz, 8.0 Gb/s, 12UI) (Note 35)

0.3

ps (rms)

QPI & SMI (100.00 MHz, 9.6 Gb/s, 12UI) (Note 35)

0.2

ps (rms)

Additive Phase Jitter,

Bypass Mode

PCIe Gen 1 (Notes 32 and 33)

10

ps (p−p)

PCIe Gen 2 Lo Band 10 kHz < f < 1.5 MHz

(Notes 32 and 36)

0.3

ps (rms)

PCIe Gen 2 High Band 1.5 MHz < f < Nyquist (50 MHz)

(Notes 32 and 36)

0.7

ps (rms)

PCIe Gen 3

(PLL BW of 2−4 MHz, CDR = 10 MHz)

(Notes 32, 34 and 36)

0.3

ps (rms)

QPI & SMI

(100.00 MHz or 133.33 MHz, 4.8 Gb/s, 6.4 Gb/s 12UI)

(Notes 35 and 36)

0.3

ps (rms)

QPI & SMI (100.00 MHz, 8.0 Gb/s, 12UI)

(Notes 35 and 36)

0.1

ps (rms)

QPI & SMI (100.00 MHz, 9.6 Gb/s, 12UI)

(Notes 35 and 36)

0.1

ps (rms)

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

31. Applies to all outputs.

32. See http://www.pcisig.com for complete specs

33. Sample size of at least 100k cycles. This figures extrapolates to 108 ps pk-pk @ 1M cycles for a BER of 1−12.

34. Subject to final ratification by PCI SIG.

35. Calculated from Intel-supplied Clock Jitter Tool v 1.6.3