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NB3W800LMNG Datasheet(PDF) 8 Page - ON Semiconductor |
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NB3W800LMNG Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 17 page NB3W800L www.onsemi.com 8 Table 13. ELECTRICAL CHARACTERISTICS – Current Consumption (VDD = VDDA = 3.3 V ±5%, TA = 0°C − 70°C), See Test Loads for Loading Conditions. (Note 35) Symbol Parameter Conditions Min Typ Max Units IDDVDD Operating Current (Note 34) 133 MHz, VDD rail 94 105 mA IDDVDDA 133 MHz, VDDA + VDDR rail, PLL Mode 38 50 mA IDDVDDPD Powerdown Current (Note 34) Power Down, VDD Rail 2.0 3.5 mA IDDVDDAPD Power Down, VDDA Rail 0.5 1.0 mA 34. Guaranteed by design and characterization, not tested in production. 35. CL = 2 pF with RS = 27 W for Zo = 85 W differential trace impedance. Table 14. ELECTRICAL CHARACTERISTICS – Skew and Differential Jitter Parameters (VDD = VDDA = 3.3 V ±5%, TA = 0°C − 70°C), See Test Loads for Loading Conditions. Symbol Parameter Conditions Min Typ Max Units tSPO_PLL CLK_IN, DIF[x:0] (Notes 36, 37, 39, 40, 43) Input−to−Output Skew in PLL mode nominal value @ 25 °C, 3.3 V −100 100 ps tPD_BYP CLK_IN, DIF[x:0] (Notes 36, 37, 39, 40, 43) Input−to−Output Skew in Bypass mode nominal value @ 25 °C, 3.3 V 2.5 4.5 ns tDSPO_PLL CLK_IN, DIF[x:0] (Notes 36, 37, 39, 40, 43) Input−to−Output Skew Varation in PLL mode across voltage and temperature −100 100 ps tDSPO_BYP CLK_IN, DIF[x:0] (Notes 36, 37, 39, 40, 43) Input−to−Output Skew Varation in Bypass mode across voltage and temperature −250 250 ps tSKEW_ALL DIF{x:0] (Notes 36, 37, 39, 43) Output−to−Output Skew across all outputs (Common to Bypass and PLL mode) 50 ps jpeak−hbw PLL Jitter Peaking (Notes 36, 42, 43) HBW_BYP_LBW# = 1 2.5 dB jpeak−lbw PLL Jitter Peaking (Notes 36, 42, 43) HBW_BYP_LBW# = 0 2 dB pllHBW PLL Bandwidth (Notes 36, 43, 44) HBW_BYP_LBW# = 1 2 3 4 MHz pllLBW PLL Bandwidth (Notes 36, 43, 44) HBW_BYP_LBW# = 0 0.7 1 1.4 MHz tDC Duty Cycle (Note 36, 46) Measured differentially, PLL and Bypass Mode 45 50 55 % tDCD Duty Cycle Distortion (Notes 36, 45) Measured differentially, Bypass Mode @ 100 MHz −2 0 2 % tjcyc−cyc Jitter, Cycle to cycle (Notes 36, 46) PLL mode 50 ps Additive Jitter in Bypass Mode 50 ps 36. CL = 2 pF with RS = 27 W for Zo = 85 W differential trace impedance. Input to output skew is measured at the first output edge following the corresponding input. 37. Measured from differential cross−point to differential cross−point. This parameter can be tuned with external feedback path, if present. 38. All Bypass Mode Input−to−Output specs refer to the timing between an input edge and the specific output edge created by it. 39. This parameter is deterministic for a given device 40. Measured with scope averaging on to find mean value. 41. t is the period of the input clock 42. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking. 43. Guaranteed by design and characterization, not tested in production. 44. Measured at 3 db down or half power point. 45. Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 46. Measured from differential waveform. Bypass mode, input duty cycle = 50%. |
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