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NB3V1102C Datasheet(PDF) 4 Page - ON Semiconductor

Part # NB3V1102C
Description  3.3V/2.5V/1.8V LVCMOS Low Skew Fanout Buffer Family
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NB3V1102C Datasheet(HTML) 4 Page - ON Semiconductor

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NB3V110xC Series
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4
Table 5. DEVICE CHARACTERISTICS Over recommended operating free−air temperature range (unless otherwise noted) (Note 4)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
OVERALL PARAMETERS FOR ALL VERSIONS
IDD
Static device current
OE = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD =
3.6 V
0.2
mA
OE = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD =
2.7 V
0.2
OE = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD =
1.89 V
0.2
IPD
Power down current
OE = 0 V; CLKIN = 0 V or VDD; IO = 0 mA; VDD =
3.6 V, 2.7 V or 1.89 V (For 1102C, 1103C, 1104C)
60
mA
OE = 0 V; CLKIN = 0 V or VDD; IO = 0 mA; VDD =
3.6 V, 2.7 V or 1.89 V (For 1106C, 1108C)
75
CPD
Power dissipation capacitance per out-
put (Note 5)
VDD = 3.3 V; f = 10 MHz
9
pF
VDD = 2.5 V; f = 10 MHz
9
VDD = 1.8 V; f = 10 MHz
9
II
Input leakage current at OE
VI = 0 V or VDD, VDD = 3.6 V or 2.7 V
± 8
mA
Input leakage current at CLKIN
± 8
Input leakage current at OE, CLKIN
VI = 0 V or VDD, VDD = 1.89 V
± 8
ROUT
Output impedance
VDD = 3.3 V
40
W
VDD = 2.5 V
45
VDD = 1.8 V
60
fOUT
Output frequency
VDD = 3.0 V to 3.6 V
DC
250
MHz
VDD = 2.3 V to 2.7 V
DC
180
VDD = 1.71 V to 1.89 V
DC
133
OUTPUT PARAMETERS FOR VDD = 3.3 V + 0.3 V
VOH
High−level output voltage
VDD = 3 V, IOH = –0.1 mA
2.9
V
VDD = 3 V, IOH = –8 mA
2.5
VDD = 3 V, IOH = –12 mA
2.2
VOL
Low−level output voltage
VDD = 3 V, IOL = 0.1 mA
0.1
V
VDD = 3 V, IOL = 8 mA
0.5
VDD = 3 V, IOL = 12 mA
0.8
tPLH, tPHL
Propagation delay (Note 6)
CLKIN to Qn
0.8
2.0
ns
tsk(o)
Output skew (Note 6)
Equal load of each output 85
°C
50
ps
Equal load of each output 105
°C
60
tr/tf
Rise and fall time
20%–80% (VOH − VOL)
0.12
0.8
ns
tDIS
Output disable time (Note 6)
OE to Qn
6
ns
tEN
Output enable time (Note 6)
OE to Qn
6
ns
tsk(p)
Pulse skew; tPLH(Qn) – tPHL(Qn) (Note 7)
To be measured with input duty cycle of 50%
180
ps
tsk(pp)
Part−to−part skew
Under equal operating conditions for two parts
0.5
ns
Tjit(f)
Additive jitter rms
12 kHz...20 MHz fOUT = 100 MHz
100
fs
12 kHz...20 MHz fOUT = 156.25 MHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. All typical values are at respective nominal VDD. For switching characteristics, outputs are terminated to 50 W to VDD/2 (see Figure 2).
5. This is the formula for the power dissipation calculation.
Ptot = Pstat + Pdyn + PCload [W] Pstat = VDD x IDD [W]
Pdyn = CPD x VDD2 x ƒ x n [W]
PCload = Cload x VDD2 x ƒ x n [W]
n = Number of switching output pins
6. With rail to rail input clock.
7. tsk(p) depends on output rise− and fall−time (tr/tf). The output duty−cycle can be calculated: odc = (tw(OUT) ± tsk(p))/tperiod; tw(OUT) is
pulse−width of ideal output waveform and tperiod is 1/fOUT.


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