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NB3N51032 Datasheet(PDF) 9 Page - ON Semiconductor |
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NB3N51032 Datasheet(HTML) 9 Page - ON Semiconductor |
9 / 13 page NB3N51032 www.onsemi.com 9 APPLICATION INFORMATION Crystal Input Interface Figure 7 shows the NB3N51032 device crystal oscillator interface using a typical parallel resonant crystal. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors, C1 and C2, need to consider the stray capacitances of the board and are used to match the nominally required crystal load capacitance CL. A parallel crystal with loading capacitance CL = 18 pF would use C1 = 26 pF and C2 = 26 pF as nominal values, assuming approximately 2 pF of stray capacitance per trace and approximately 8 pF of internal capacitance. CL = (C1 + Cstray + Cin) / 2; C1 = C2 The frequency accuracy and duty cycle skew can be fine-tuned by adjusting the C1 and C2 values. For example, increasing the C1 and C2 values will reduce the operational frequency. Figure 7. Crystal Interface Loading C1 = 26 pF C2 = 26 pF X1 X2 Fundamental Mode Parallel Resonant Crystal 18 pF Load Power Supply Filter In order to isolate the NB3N51032 from system power supply, noise decoupling is required. The 10 mF and a 0.1 mF cap from supply pins to GND decoupling capacitor has to be connected between VDD (pins 12 and 16) and GND (pins 7 and 13). It is recommended to place decoupling capacitors as close as possible to the device to minimize lead inductance. Termination The output buffer structure is shown in the Figure 8. Figure 8. Simplified Output Structure RREF CLKx CLKx IREF 2.6 mA 475 W HCSL / LVDS termination 14 mA |
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