6.42

IDT70T35/34L(IDT70T25/24L)

PRELIMINARY

High-Speed 2.5V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

10

NOTES:

1. Timing depends on which signal is asserted last,

OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first,

CE, OE, LB, or UB.

BUSY has no

relation to valid output data.

5.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).

2.

This parameter is guaranteed by device characterization, but is not production tested.

3.

To access RAM,

70T35/34L20

(70T25/24L20)

Com'l Only

70T35/34L25

(70T25/24L25)

Com'l

& Ind

Unit

Symbol

Parameter

Min.

Max.

Min.

Max.

READ CYCLE

Read Cycle Time

20

____

25

____

ns

Address Access Time

____

20

____

25

ns

____

20

____

25

ns

Byte Enable Access Time

(3)

____

20

____

25

ns

Output Enable Access Time

(3)

____

12

____

13

ns

Output Hold from Address Change

3

____

3

____

ns

3

____

3

____

ns

____

12

____

15

ns

0

____

0

____

ns

____

20

____

25

ns

Semaphore Flag Update Pulse (

OE or SEM)10

____

10

____

ns

Semaphore Address Access

(3)

____

20

____

25

ns

5639 tbl 11

R/

W

CE

ADDR

OE

UB, LB

5639 drw 08

(4)

(4)

(4)

(4)

(1)

(2)

(3,4)

VALID DATA

(4)