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IDT72V3622L15PQF Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT72V3622L15PQF Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 29 page  10 IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURERANGE Following Reset, the level applied to the FWFTinputtochoosethedesired timing mode must remain static throughout FIFO operation. Refer to Figure 2 (Reset) for a First Word Fall Through select timing diagram. ALMOST-EMPTYFLAGANDALMOST-FULLFLAGOFFSETPROGRAM- MING Four registers in these devices are used to hold the offset values for the Almost-EmptyandAlmost-Fullflags.TheportBAlmost-Emptyflag( AEB)Offset register is labeled X1 and the port A Almost-Empty flag ( AEA) Offset register is labeled X2. The port A Almost-Full flag ( AFA) Offset register is labeled Y1 and the port B Almost-Full flag ( AFB) Offset register is labeled Y2. The index ofeachregisternamecorrespondstoitsFIFOnumber.Theoffsetregisterscan be loaded with preset values during the reset of a FIFO or they can be programmed from port A (see Table 1). FS0 and FS1 function the same way in both IDT Standard and FWFT modes. — PRESET VALUES ToloadtheFIFO'sAlmost-EmptyflagandAlmost-FullflagOffsetregisters withoneofthethreepresetvalueslistedinTable1,atleastoneoftheflagselect inputs must be HIGH during the LOW-to-HIGH transition of its reset input. For example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be HIGH when FlFO1 Reset ( RST1) returns HIGH. Flag offset registers associatedwithFIFO2areloadedwithoneofthepresetvaluesinthesameway with FIFO2 Reset ( RST2)toggledsimultaneouslywithFIFO1Reset(RST1). For preset value loading timing diagram, see Figure 2. — PARALLEL LOAD FROM PORT A ToprogramtheX1,X2,Y1,andY2registersfromportA,bothFlFOsshould be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH transition of the Reset inputs. After this reset is complete, the first four writes to FIFO1 do not store data in the FIFO memory but load the offset registers in the order Y1, X1, Y2, X2. The port A data inputs used by the offset registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT72V3622, IDT72V3632, or IDT72V3642, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers ranges from 1 to 252 for the IDT72V3622; 1 to 508 for the IDT72V3632; and 1 to 1,020 for the IDT72V3642. After all the offset registers are programmed from port A, the port B Full/Input Ready flag ( FFB/IRB)isset HIGH, and both FIFOs begin normal operation. See Figure 3 for relevant offset register parallel programming timing diagram. SIGNAL DESCRIPTION RESET Afterpowerup,aMasterResetoperationmustbeperformedbyproviding a LOW pulse to RST1 and RST2 simultaneously. Afterwards, the FIFO memories of the IDT723622/723632/723642 are reset separately by taking their Reset ( RST1, RST2) inputs LOW for at least four port-A Clock (CLKA) andfourport-BClock(CLKB)LOW-to-HIGHtransitions. TheResetinputscan switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the Input Ready flag (IRA, IRB) LOW, the Output Ready flag (ORA, ORB) LOW, the Almost-Empty flag ( AEA, AEB) LOW, and the Almost-Full flag ( AFA, AFB) HIGH. Resetting a FIFO also forces the Mailbox Flag ( MBF1, MBF2) of the parallel mailbox register HIGH. After a FIFO is reset, its Input Ready flag is set HIGH after two clock cycles to begin normal operation. A LOW-to-HIGH transition on a FIFO Reset ( RST1,RST2)inputlatches the value of the Flag Select (FS0, FS1) inputs for choosing the Almost-Full and Almost-Empty offset programming method. (For details see Table 1, Flag Programming,andtheProgrammingtheAlmost-EmptyandAlmost-FullFlags section). The relevant FIFO Reset timing diagram can be found in Figure 2. FIRST WORD FALL THROUGH ( FWFT) After Master Reset, the FWFT select function is active, permitting a choice between two possible timing modes: IDT Standard mode or First Word Fall Through (FWFT) mode. Once the Reset ( RST1, RST2) input is HIGH, a HIGH on the FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select IDT Standard mode. This mode uses the Empty Flag function ( EFA, EFB) to indicate whether or not there are any words present in the FIFO memory. It uses the Full Flag function ( FFA, FFB) to indicate whether or not the FIFO memory has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using a formal read operation. Once the Reset ( RST1, RST2) input is HIGH, a LOW on the FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready function (ORA, ORB) to indicate whether or not there is valid data at the data outputs (A0-A35orB0-B35).ItalsousestheInputReadyfunction(IRA,IRB)toindicate whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to data outputs, no read request necessary. Subsequent words must be accessed by performing a formal read operation. NOTES: 1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA. 2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB. FS1 FS0 RST1 RST2 X1 AND Y1 REGlSTERS(1) X2 AND Y2 REGlSTERS(2) HH ↑ X64 X HH X ↑ X64 HL ↑ X16 X HL X ↑ X16 LH ↑ X8 X LH X ↑ X8 LL ↑↑ Parallel programming via Port A Parallel programming via Port A TABLE 1 .LAG PROGRAMMING |
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