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BD6164GUT Datasheet(PDF) 6 Page - Rohm |
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BD6164GUT Datasheet(HTML) 6 Page - Rohm |
6 / 21 page Datasheet Datasheet 6/17 www.rohm.com © 2012 ROHM Co., Ltd. All rights reserved. TSZ22111 ・15・001 TSZ02201-0G3G0C200280-1-2 21.Dec.2012 Rev.001 BD6164GUT ● Timing diagram SDA SCL t SU;DAT t LOW S Sr P S t BUF t SP t HD;STA t SU;STA t HIGH t HD;STA t f t r t HD;DAT t SU;STO t r t f Figure 7. I 2C timing diagram ● Electrical Characteristics (Unless otherwise specified, Ta=25 oC, V TH,H1=1.8V / VTH,L1=0V) Parameter Symbol Spec Unit Min. Typ. Max. SCL clock frequency fSCL 0 - 400 kHz Rise/fall times SDA/SCL tf / tf - - 300 ns LOW period of the SCL clock tLOW 1.3 - - μs HIGH period of the SCL clock tHIGH 0.6 - - μs Hold time (repeated) START condition Hold time for a repeated START condition tHD;STA 0.6 - - μs Set-up time for a repeated START condition tSU;STA 0.6 - - μs Data hold time tHD;DAT 0.1 - 0.9 μs Data set-up time tSU;DAT 100 - - ns Set-up time for STOP condition tSU;STO 0.6 - - μs Bus free time between a STOP and START condition tBUF 1.3 - - μs |
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