TMS626812

1048576 BY 8-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SMOS687A –JULY 1996 – REVISED APRIL 1997

7

POST OFFICE BOX 1443

burst sequence (continued)

Table 6. 8-Bit Burst Sequences

INTERNAL COLUMN ADDRESS A2 – A0

DECIMAL

BINARY

START

2ND

3RD

4TH

5TH

6TH

7TH

8TH

START

2ND

3RD

4TH

5TH

6TH

7TH

8TH

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

1

2

3

4

5

6

7

0

001

010

011

100

101

110

111

000

2

3

4

5

6

7

0

1

010

011

100

101

110

111

000

001

Serial

3

4

5

6

7

0

1

2

011

100

101

110

111

000

001

010

Serial

4

5

6

7

0

1

2

3

100

101

110

111

000

001

010

011

5

6

7

0

1

2

3

4

101

110

111

000

001

010

011

100

6

7

0

1

2

3

4

5

110

111

000

001

010

011

100

101

7

0

1

2

3

4

5

6

111

000

001

010

011

100

101

110

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

1

0

3

2

5

4

7

6

001

000

011

010

101

100

111

110

2

3

0

1

6

7

4

5

010

011

000

001

110

111

100

101

Interleave

3

2

1

0

7

6

5

4

011

010

001

000

111

110

101

100

Interleave

4

5

6

7

0

1

2

3

100

101

110

111

000

001

010

011

5

4

7

6

1

0

3

2

101

100

111

110

001

000

011

010

6

7

4

5

2

3

0

1

110

111

100

101

010

011

000

001

7

6

5

4

3

2

1

0

111

110

101

100

011

010

001

000

latency

The beginning data-out cycle of a read burst can be programmed to occur two or three CLK cycles after the read

command (see the section on setting the mode register, page 9). This feature allows adjustment of the device

so that it operates using the capability to latch the data output from the ’626812. The delay between the READ

command and the beginning of the output burst is known as CAS latency. After the initial output cycle begins,

the data burst occurs at the CLK frequency without any intervening gaps. Use of minimum read latencies is

restricted, based on the maximum frequency rating of the ’626812.

There is no latency for data-in cycles (write latency). The first data-in cycle of a write burst is entered at the same

rising edge of CLK on which the WRT command is entered. The write latency is fixed and is not determined by

the mode-register contents.

two-bank operation

The ’626812 contains two independent banks that can be accessed individually or in an interleaved fashion.

Each bank must be activated with a row address before it can be accessed. Each bank must then be deactivated

before it can be activated again with a new row address. The bank-activate / row-address-entry command

(ACTV) is entered by holding RAS low, CAS high, W high, and A11 valid on the rising edge of CLK. A bank can

be deactivated either automatically during a READ-P or a WRT-P command or by use of the deactivate-bank

(DEAC) command. Both banks can be deactivated at once by use of the DCAB command (see Table 1 and the

section on bank deactivation description, page 8).