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XR16C2850IP40 Datasheet(PDF) 5 Page - Exar Corporation |
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XR16C2850IP40 Datasheet(HTML) 5 Page - Exar Corporation |
5 / 43 page XR16C2850 3.3V AND 5V DUART WITH 128-BYTE FIFO áç áç áç áç REV. 2.0.0 5 Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. CLKSEL - - 25 I Clock Pre-scaler select. Connect to VCC for divide by 1 (default) and GND for divide by 4. MCR[7] can override the state of this pin following reset or initialization. See Figure 6 and MCR[7]. CLK8/16 - - 24 I Transmit/Receive data sampling rate. Connect to VCC for normal 16X sampling clock (standard baud rates, default) or GND for 8X sampling clock to double the standard baud rates, 2X. RESET 35 39 36 I Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will reset the internal registers and all outputs. The UART transmitter output will be held at logic 1, the receiver input will be ignored and outputs are reset during reset period (see External Reset Conditions). VCC 40 44 42 Pwr 3.3V or 5V power supply. Please note that the inputs are not 5V tolerant when operating at 3.3V. GND 20 22 17 Pwr Power supply common, ground. N.C. none none 12 No Connection. These pins are open, but typically, should be connected to GND for good design practice. NAME 40-PDIP PIN # 44-PLCC PIN # 48-TQFP PIN # TYPE DESCRIPTION |
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