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XR16C2850CP40 Datasheet(PDF) 3 Page - Exar Corporation |
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XR16C2850CP40 Datasheet(HTML) 3 Page - Exar Corporation |
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3 / 43 page  XR16C2850 3.3V AND 5V DUART WITH 128-BYTE FIFO áç áç áç áç REV. 2.0.0 3 PIN DESCRIPTIONS NAME 40-PDIP PIN # 44-PLCC PIN # 48-TQFP PIN # TYPE DESCRIPTION DATA BUS INTERFACE A2 A1 A0 26 27 28 29 30 31 26 27 28 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. D7 D6 D5 D4 D3 D2 D1 D0 8 7 6 5 4 3 2 1 9 8 7 6 5 4 3 2 3 2 1 48 47 46 45 44 I/O Data bus lines [7:0] (bidirectional). IOR# 21 24 19 I Input/Output Read Strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed to by the address lines A2:A0. The data byte is placed on the data bus to allow the host processor to read it on the rising edge. IOR# must never be active together with IOW#. IOW# 18 20 15 I Input/Output Write Strobe (active low). The falling edge instigates an internal write cycle and the rising edge transfers the data byte on the data bus to an internal reg- ister pointed by the address lines. IOW# must never be active together with IOR#. CSA# CSB# 14 15 16 17 10 11 I UART channel select (active low) to enable UART chan- nel A or B in the device for data bus operation. INTA INTB 30 29 33 32 30 29 O UART channel A or B Interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTA or INTB is set to the active mode and OP2A# or OP2B# output to a logic 0 when MCR[3] is set to a logic 1. INTA or INTB is set to the three state mode and OP2A# or OP2B# to a logic 1 when MCR[3] is set to a logic 0 (default). See MCR[3]. TXRDYA# TXRDYB# - - 1 12 43 6 O UART channel A or B Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel A or B. See Table 2 on page 8. If it is not used, leave it unconnected. RXRDYA# RXRDYB# - - 34 23 31 18 O UART channel A or B Receiver Ready (active low). This output provides the RX FIFO/RHR status for receive channel A or B. See Table 2 on page 8. If it is not used, leave it unconnected. MODEM OR SERIAL I/O INTERFACE TXA TXB 11 12 13 14 7 8 O UART channel A or B Transmit Data or infrared encoder data. Standard transmit and receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic 1 during reset or idle (no data). Infrared IrDA trans- mit and receive interface is enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is a logic 0. If it is not used, leave it unconnected. |
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