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TMS28F010A-10C3NL4 Datasheet(PDF) 7 Page - Texas Instruments |
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TMS28F010A-10C3NL4 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 22 page TMS28F010A 1048576-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 command register The command register controls the program and erase functions of the TMS28F010A. The algorithm-selection mode can be activated using the command register in addition to the above method. When VPP is high, the contents of the command register and the function being performed can be changed. The command register is written to when E is low and W is pulsed low. The address is latched on the leading edge of the pulse, while the data is latched on the trailing edge. Accidental programming or erasure is minimized because two commands must be executed to invoke either operation. power supply considerations Each device should have a 0.1- µF ceramic capacitor connected between VCC and VSS to suppress circuit noise. Changes in current drain on VPP require it to have a bypass capacitor as well. Printed-circuit traces for both power supplies should be appropriate to handle the current demand. Table 2. Command Definitions COMMAND REQUIRED BUS FIRST BUS CYCLE SECOND BUS CYCLE COMMAND BUS CYCLES OPERATION† ADDRESS DATA OPERATION† ADDRESS DATA Read 1 Write X 00h Read RA RD Algorithm-Selection Mode 3 Write X 90h Read 0000 0001 89h B4h Set-Up-Erase/Erase 2 Write X 20h Write X 20h Erase Verify 2 Write EA A0h Read X EVD Set-Up-Program/Program 2 Write X 40h Write PA PD Program Verify 2 Write X C0h Read X PVD Reset 2 Write X FFh Write X FFh † Modes of operation are defined in Table 1. Legend: EA Address of memory location to be read during erase verify. RA Address of memory location to be read. PA Address of memory location to be programmed. Address is latched on the falling edge of W. RD Data read from location RA during the read operation. EVD Data read from location EA during erase verify. PD Data to be programmed at location PA. Data is latched on the rising edge of W. PVD Data read from location PA during program verify. |
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