W39L040

Publication Release Date: February 10, 2003

- 7 -

Revision A3

Write Operation Status

DQ7: Data Polling

The W39L040 device features Data Polling as a method to indicate to the host that the embedded

algorithms are in progress or completed.

During the Embedded Program Algorithm, an attempt to read the device will produce the complement

of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to

read the device will produce the true data last written to DQ7.

During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7

output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce

a "1" at the DQ7 output.

For chip erase, the Data Polling is valid after the rising edge of the sixth pulse in the six #WE write

pulse sequences. For sector erase, the Data Polling is valid after the last rising edge of the sector

erase #WE pulse. Data Polling must be performed at sector addresses within any of the sectors being

erased. Otherwise, the status may not be valid.

Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously

while the output enable (#OE) is asserted low. This means that the device is driving status information

on DQ7 at one instant of time and then that byte

′s valid data at the next instant of time. Depending on

when the system samples the DQ7 output, it may read the status or valid data. Even if the device has

completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0 –

DQ6 may be still invalid. The valid data on DQ0

− DQ7 will be read on the successive read attempts.

The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded

Erase Algorithm, or sector erase time-out (see "Command Definitions").

DQ6: Toggle Bit

The W39L040 also features the "Toggle Bit" as a method to indicate to the host system that the

embedded algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling)

data from the device at any address will result in DQ6 toggling between one and zero. Once the

Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will

be read on the next successive attempt. During programming, the Toggle Bit is valid after the rising

edge of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid

after the rising edge of the sixth #WE pulse in the six write pulse sequence. For sector/page erase, the

Toggle Bit is valid after the last rising edge of the sector/page erase #WE pulse. The Toggle Bit is

active during the sector/page erase time-out.

Either #CE or #OE toggling will cause DQ6 to toggle.