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VSC8122 Datasheet(PDF) 4 Page - Vitesse Semiconductor Corporation |
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VSC8122 Datasheet(HTML) 4 Page - Vitesse Semiconductor Corporation |
4 / 14 page Data Sheet VSC8122 Multi-Rate SONET/SDH Clock and Data Recovery IC VITESSE SEMICONDUCTOR CORPORATION Page 4 G52228-0, Rev 4.1 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Two sets of reference frequencies for the VSC8122 are shown in Table 2. SONET reference clock frequen- cies are as indicated, with Gigabit Ethernet frequencies listed in parenthesis. The two different sets of reference clocks are needed since the reference clock for SONET and Gigabit Ethernet applications will be slightly differ- ent. Internally, the VSC8122 requires a 19.44MHz reference (or 19.53MHz reference for Gigabit Ethernet). The customer can select to provide either the 19.44MHz reference (or 19.53MHz reference for Gigabit Ethernet), or the 2x, 4x or 8x of that reference at 38.88MHz (39.06MHz), 77.76MHz (78.13MHz) or 155MHz (156.25MHz). The REF_SEL[1:0] inputs will program the internal divider as required to use the selected REFCK frequency. Two reference clock inputs are provided, REFCK1 and REFCK0, to allow “on-the-fly switching” between SONET and Gigabit Ethernet applications if desired. Since SONET and Gigabit Ethernet require different refer- ence clock frequencies, the VSC8122 allows the user to toggle between the two reference clock frequencies (REFCK1 and REFCK0) to supply the appropriate input clock. REF_INPUTSEL is used to toggle between the two reference clock input frequencies; REF_INPUTSEL= “0” selects REFCK0 and REF_INPUTSEL= “1” selects REFCK1. Either reference clock input (REFCK1, REFCK0) can be used for SONET or Gigabit Ethernet reference frequencies. LVPECL levels are recommended for REFCK inputs (see Figure 4). If a reference clock is unused, it is recommended that one of its inputs be tied to VCC through a 5.1kΩ resistor, the other one to GND through a 5.1k Ω resistor. Figure 4: REFCK Input Levels REFCK0 / VSC8122 VSC8122 0.1µf REFCK0 / REFCK1 REFCK1 LVPECL Level REFCK Inputs (recommended) NON- LVPECL Level REFCK Inputs 50 Ω VCC-2 (1) 50 Ω VTERM (1, 2) NOTES: (1) For differential REFCK input signals, 100 Ω termination between true and complement REFCK signals can be substituted for the 50 Ω to V TERM termination on each line. (2) With the input ac-coupled, VTERM can be to any power supply required for the upstream device. |
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