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ADRF6720-27ACPZ-R7 Datasheet(PDF) 8 Page - Analog Devices |
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ADRF6720-27ACPZ-R7 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 44 page  Data Sheet ADRF6720-27 Rev. B | Page 7 of 43 Parameter Test Conditions/Comments Min Typ Max Unit BASEBAND INPUTS I± and Q± pins I and Q Input DC Bias Level 2.68 V Bandwidth 1 dB >1000 MHz Differential Input Impedance Frequency = 100 MHz2 55 KΩ Differential Input Capacitance Frequency = 100 MHz2 0.97 pF OUT ENABLE ENBL pin Turn-On Settling Time ENBL low to high (90% of envelope), when Register 0x01[10] = 1, Register 0x10[10] = 1 170 ns Turn-Off Settling Time ENBL high to low (10% of envelope), when Register 0x01[10] = 1, Register 0x10[10] = 1 10 ns DIGITAL LOGIC SCLK, SDIO, CS, and ENBL Input Voltage High (VIH) 1.4 V Input Voltage Low (VIL) 0.7 V Input Current (IIH/IIL) −1 +1 µA Input Capacitance (CIN) 5 pF Output Voltage High (VOH) IOH = −100 µA 2.3 V Output Voltage Low (VOL) IOL = +100 µA 0.2 V POWER SUPPLIES Voltage Range VPOSx 3.3 V Supply Current Tx mode at internal LO mode (PLL, internal VCO , and modulator enabled, LO output driver disabled) 425 mA Tx mode at external 1× LO mode (PLL, internal VCO disabled, modulator enabled, LO output driver disabled) 218 mA LO output driver; LO_DRV_LVL bits (Register 0x22[7:6]) = 10 42 mA Power-down mode 14.5 mA 1 The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10log10(fPFD) − 20log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 153.6 MHz, fREF power = 4 dBm with a 38.4 MHz fPFD. The FOM was computed at a 50 kHz offset. 2 Refer to Figure 47 for a plot of input impedance over frequency. TIMING CHARACTERISTICS Table 2. Parameter Description Min Typ Max Unit tSCLK Serial clock period 38 ns tDS Setup time between data and rising edge of SCLK 8 ns tDH Hold time between data and rising edge of SCLK 8 ns tS Setup time between falling edge of CS and SCLK 10 ns tH Hold time between rising edge of CS and SCLK 10 ns tHIGH Minimum period that SCLK should be in a logic high state 10 ns tLOW Minimum period that SCLK should be in a logic low state 10 ns tACCESS Maximum time delay between falling edge of SCLK and output data valid for a read operation 13 ns tz Maximum time delay between CS deactivation and SDIO bus return to high impedance 5 ns Figure 2. Serial Port Timing Diagram tS tDS tDH tHIGH tLOW tSCLK tH DON'T CARE DON'T CARE A5 A4 A3 A2 A1 A0 D15 D14 D13 D3 D2 D1 D0 DON'T CARE DON'T CARE SCLK SDIO R/W tZ tACCESS A6 CS |
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