CDK8307 datasheet(2/31 Pages) EXAR

Part #	CDK8307

Description	12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS

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Manufacturer	EXAR [Exar Corporation]

Direct Link	http://www.exar.com

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2 / 31 page

Data Sheet

2/31

Rev 1C

Table of Contents

Features .................................................................. 1

Applications ............................................................ 1

General Description................................................ 1

Block Diagram ........................................................ 1

Table of Contents ................................................... 2

Ordering Information............................................. 3

Pin Configurations.................................................. 4

Pin Assignments .................................................. 5-8

Absolute Maximum Ratings ................................... 9

Reliability Information........................................... 9

ESD Protection........................................................ 9

Recommended Operating Conditions.................... 9

Electrical Characteristics...................................... 10

Electrical Characteristics – CDK8307A............10-11

Electrical Characteristics – CDK8307B................ 11

Electrical Characteristics – CDK8307C............11-12

Electrical Characteristics – CDK8307D............12-13

Electrical Characteristics – CDK8307E ................ 13

Digital and Timing Electrical Characteristics ..13-14

LVDS Timing Diagrams......................................... 15

Figure 1. 12-bit Output, DDR Mode......................... 15

Figure 2. 14-bit Output, DDR Mode......................... 15

Figure 3. 12-bit Output, SDR Mode......................... 15

Figure 4. Data Timing............................................ 15

Serial Interface..................................................... 16

Timing Diagram .................................................... 16

Figure 5. Serial Port Interface Timing Diagram..... 16

Table 1. Serial Port Interface Timing Definitions ... 16

Register Initialization ............................................. 16

Serial Register Map ..........................................17-18

Table 2. Summary of Functions Supported

by Serial Interface ................................17-18

Description of Serial Registers ........................18-25

Table 3. Software Reset ......................................... 18

Table 4. Power-Down Modes .................................. 18

Table 5. LVDS Drive Strength Programmability......... 19

Table 6. LVDS Output Drive Strength for

LCLK, FCLK, and Data ............................... 19

Table 7. LVDS Internal Termination

Programmability ....................................... 20

Table 8. LVDS Output Internal Termination.............. 20

Table 9. Analog Input Invert................................... 20

Table 10. LVDS Test Patterns.................................. 21

Table 11. Programmable Gain................................. 21

Table 12. Gain Setting for Channels 1-8 .................. 22

Table 13. LVDS Clock Programmability and

Data Output Modes................................. 22

Figure 6. Phase Programmability Modes for LCLK..... 23

Figure 7. SDR Interface Modes ............................... 23

Table 14. Number of Serial Output Bits ................... 23

Figure 8. LVDS Output Timing Adjustment .............. 24

Table 15. Full Scale Control .................................... 24

Table 16. Register Values with Corresponding

Charge in Full-Scale Range ...................... 25

Table 17. Clock Frequency...................................... 25

Table 18. Clock Frequency Settings......................... 25

Table 19. Performance Control................................ 25

Table 20. Performance Control Settings................... 26

Table 21. External Common Mode Voltage

Buffer Driving Strength ........................... 26

Theory of Operation ............................................. 27

Recommended Usage........................................... 27

Analog Input......................................................... 27

Figure 9. Input Configuration Diagram ................ 27

DC-Coupling.......................................................... 27

Figure 10. DC-Coupled Input .............................. 27

AC-Coupling.......................................................... 28

Figure 11. Transformer Coupled Input ................. 28

Figure 12. AC-Coupled Input .............................. 28

Figure 13. Alternative Input Network................... 28

Clock Input and Jitter Considerations ...................... 29

Mechanical Dimensions ...................................30-31

QFN-64 Package.................................................... 30

TQFP-80 Package .................................................. 31

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