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ML7202-001 Datasheet(PDF) 11 Page - LAPIS Semiconductor Co., Ltd. |
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ML7202-001 Datasheet(HTML) 11 Page - LAPIS Semiconductor Co., Ltd. |
11 / 65 page FEDL7202-001-01 ML7202-001 11/65 (64ms) (64ms) (e) (e) (f) (f) (a) (a) (b) (b) (d) (d) (c) (c) (c) (d) (a) (b) (d) (c) (b) (a) Channel 1 echo canceller (64ms) PCMLNO1 PCMLNI1 Input control Output control SYNCL, BCLKL PCMACO1 PCMACI1 PCMADO1 PCMADI1 IS1 IR1 Channel 1 ADPCM transcoder Input control Output control Input control Output control Input control Output control Channel 2 echo canceller (64ms) Input control Output control Channel 2 ADPCM transcoder Input control Output control Input control Output control Input control Output control SYNCA, BCLKA PCMLNO2 PCMLNI2 PCMACO2 PCMACI2 PCMADO2 PCMADI2 IS2 IR2 IOSEL(CR0-B3)=0 Control (a): CONTA1 (channel 1 ADPCM through control)...CR2-B7 Control (b): CONTA2 (channel 2 ADPCM through control)...CR3-B7 Control (c): DTHR1 (channel 1 end-to-end 4-bit ADPCM transparent control)...CR2-B5 Control (d): DTHR2 (channel 2 end-to-end 4-bit ADPCM transparent control)...CR3-B5 Control (e): LTHR1 (channel 1 echo canceller through control)...CR27-B7 Control (f): LTHR2 (channel 2 echo canceller through control)...CR28-B7 Channel 1 ADPCM CODEC Time Slot setting: CR13-B4 to B0 Channel 2 ADPCM CODEC Time Slot setting: CR14-B4 to B0 Channel 1 PCM CODEC Time Slot setting: CR11-B4 to B0 Channel 2 PCM CODEC Time Slot setting: CR12-B4 to B0 (c) (c) (d) (d) "0" "0" "1" "1" "1" "1" "0" "0" "1" "0" "1" "0" "1" "0" "1" "0" "0" "1" "0" "1" "0" "0" "1" "1" Note: Fix the input pins, PCMACI1, PCMADI1, PCMACI2, and PCMADI2 to “1” or “0”. The outputs of PCMACO1, PCMADO1, PCMACO2 and PCMADO2 are all in high impedance. Figure 1 Signal Input/Output Control 1 |
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