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FEDL7029-04 Datasheet(PDF) 9 Page - LAPIS Semiconductor Co., Ltd. |
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FEDL7029-04 Datasheet(HTML) 9 Page - LAPIS Semiconductor Co., Ltd. |
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9 / 29 page  FEDL7029-04 ML7029 9/29 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power Supply Voltage VDD — –.3 to +5.0 V Analog Input Voltage VAIN — –0.3 to VDD+0.3 V Digital Input Voltage VDIN — –0.3 to VDD+0.3 V Storage Temperature Tstg — –55 to +150 C RECOMMENDED OPERATION CONDITIONS Parameter Symbol Condition Min. Typ. Max. Unit Power Supply Voltage VDD Voltage must be fixed +2.7 3.0 +3.6 V Operating Temperature Range Ta — –25 +25 +70 C Digital Input High Voltage VIH Digital Input Pins 0.45 VDD — VDD V Digital Input Low Voltage VIL Digital Input Pins 0 — 0.16 VDD V Master Clock Frequency fMCK1 MCK 7.776 10.368 20.736 MHz Master Clock Frequency Accuracy fMCK2 MCK –0.01% SYNC 1296 +0.01% MHz Bit Clock Duty fBCK BCLK SYNC 8— SYNC 256 kHz Sampling Frequency (*1) fSYNC SYNC 6.0 8.0 16 kHz Master Clock Duty Ratio DMCK MCK (20.736 MHz) 30 50 70 % Clock Duty Ratio DCLK BCLK, EXCK 30 50 70 % Digital Input Rise Time tir Digital Input Pins — — 50 ns Digital Input Fall Time tif Digital Input Pins — — 50 ns PCM Sync Signal Setting Time (Continuous BCLK) tBS BCLK SYNC (see Fig. 3-1) 100 — — ns PCM Sync Signal Setting Time (Burst Mode Clock) tSB BCLK SYNC (see Fig. 3-2) 0 — 20 s SYNC Signal Width (Continuous BCLK) tWS SYNC (see Fig. 3-1) 1BCLK — SYNC –1 BCLK s SYNC Signal Width (Burst Mode Clock) tWSB SYNC (see Fig. 3-2) 1BCLK — Burst Clock –1 s PCM, ADPCM Setup Time tDS — 100 — — ns PCM, ADPCM Hold Time tDH — 100 — — ns Digital Output Load CDL Digital Output Pins — — 100 pF Bypass Capacitors for SG CSG SG to AG 10+0.1 — — F *1: Refer to the Appendix. |
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