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ML620Q154A Datasheet(PDF) 2 Page - LAPIS Semiconductor Co., Ltd. |
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ML620Q154A Datasheet(HTML) 2 Page - LAPIS Semiconductor Co., Ltd. |
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2 / 36 page  FEDL620Q150A-01 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A 2/36 • Time base counter − Low-speed time base counter × 1 channel • Watchdog timer − Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second − Free running − Overflow period: 4 types selectable (125ms, 500ms, 2s, 8s @32.768kHz) • Timers − 8 bits × 2ch (16-bits configuration available × 1ch) − 16 bits × 4ch • PWM − 16bits × 4ch − The auto reload timer mode / PWM mode − Timer start-stop function by the software and an external trigger. − A pulse width can be measured using an external-trigger input. − An external event can be selected as the counter clock. − Complement synchronous PWM • Synchronous serial port − 1ch − Master/slave selectable − LSB first/MSB first selectable − 8-bit length/16-bit length selectable • UART − Full-duplex × 1ch ( Half-duplex × 2ch ) − Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits − Positive logic/negative logic selectable − Built-in baud rate generator • I2C bus interface − Master function only − Fast mode (400kbit/s), Standard mode (100kbit/s) • Successive approximation type A/D converter − 10-bit A/D converter − Input: 12ch （Maximum） − Conversion time: 43us, 13.5µs per channel (conversion-time is selectable) • Analog Comparator − 1ch − Edge for the interrupt and sampling function is selectable. |
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